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- A head-to-head comparison of the ARM Cortex-M4 and –M0 processor cores by Jack Ganssle
- Friday Video: SoC in tiny 500mg backpack transforms cockroach into radio-controlled exploration vehicle
- Friday Video: A different kind of fab with some very, very cool machines
- Friday Video: Get the latest skinny on the IPC-2581 open interchange standard for PCB design
- Smartphones: Where PCIe has not gone before—but will. Sooner rather than later.
EDA360 Tag Cloud2.5D 3D 3D IC 20nm 28nm 32nm 40nm Agilent Altera AMD Analog Android Apple ARM ARM architecture ARM Cortex-A15 ASIC Broadcom Cadence Canon Cortex Cortex-A15 Cortex-M0 DAC Dave Jones DDR3 DDR4 Double Patterning EDA EDPS Field-programmable gate array FinFET Flash Flash memory FPGA Freescale Freescale Semiconductor GlobalFoundries Google IBM Intel IP iPad iPhone JEDEC Jim Hogan Kinect Linux Low Power Lytro microcontroller Micron Microsoft Mixed Signal Multi-core processor Nvidia OrCAD pcb Printed circuit board Qualcomm Robot Samsung SDRAM Snapdragon SoC STMicroelectronics SystemC Texas Instruments TI TSMC USB verification video Wide I/O Xilinx
- A head-to-head comparison of the ARM Cortex-M4 and –M0 processor cores by Jack Ganssle
- Ingenious architectural features allow ST to extract maximum performance from new microcontroller family based on ARM Cortex-M4. Cost: less than 6 bucks in 1000s
- 3D Thursday (early): Steve’s Improbable History of 3D ICs? Six decades of 3D electronic packaging
- Download a free PDF of the Mixed-signal Methodology Guide, Chapter 1: Design Trends and Challenges
- 3D Thursday: Intel Penwell SoC for mobile phones employs POP (package-on-package) LPDDR2 SDRAM to reduce power
- How about a quick and easy guide to ARM Cortex processor cores? Got one for you from ARM TechCon 2011
- 3D Thursday: 28nm design and 2.5D packaging saves Xilinx a ton of power. You can too even if you're not designing FPGAs!
- Friday Video: Want the basics of PCB design in 45 minutes? Dave Jones delivers yet again with a free tutorial.
- 3D Week: Wide I/O SDRAM, Network on Chip, Multicore, TSV, Asynchronous Logic—3D SoC stack from CEA-Leti and ST-Ericsson hits all the advanced notes. Can you say “Tour de Force”?
- Qualcomm reveals more Snapdragon 4 SoC details in a White Paper. Want to know what’s inside?
Download the EDA360 Vision Paper here:
Category Archives: IP
Today, MSNBC’s Technolog carries an article by Henry Blodget that discusses another aftermath of the Amazon EC2 (Elastic Compute Cloud) services failure: lost data. The article quotes a letter from Amazon stating: “A few days ago we sent you an … Continue reading
On Friday, Altera posted a video that shows the company characterizing some of the features of the upcoming Stratix V FPGA, being built with a 28nm process technology. The largest member of the Stratix V FPGA family will incorporate nearly … Continue reading
We talk endlessly about multi-processor SoCs (MPSoCs) but give little attention to memory. Memory is a given. Really? Not, not really. Today’s processor cores have a voracious appetite for memory. They need plenty of memory to shovel instructions into the … Continue reading
Today, Cadence introduced three critical IP components that support the Wide I/O memory interface. These components include a configurable memory controller, a Wide I/O PHY, and appropriate verification IP. You can read more about this announcement in Richard Goering’s “Industry … Continue reading
Earlier this month, I wrote a blog entry about the number of people it takes to design an SoC. (See “How many people does it take to design an SoC? Perspectives from Ron Collett and the EDA360 Insider”.) Since then, … Continue reading
Experienced EDA entrepreneur Jim Hogan has been attending DATE (Design Automation and Test Europe, the European version of DAC) this week in Grenoble and he’s written an account and analysis of an IP panel at the event. (Cadence CMO John … Continue reading
Eric Esteve just published an article over at SemiWiki titled “IP would be nothing without VIP…” that provides a good background of VIP and some analysis of the market. Check it out here.
A pointer on http://www.design-reuse.com led to some excellent videos from the Embedded World event in Germany last week. The videos are from the Xilinx booth at Embedded World and show the pre-silicon emulation boards Xilinx has developed for the Zynq … Continue reading
The man who’s probably done as much primary research on EDA and best ASIC design practices as anyone in the business, Ron Collett, just published an article in EE Times titled “Optimal team sizes for chip projects.” In his article, … Continue reading
Cadence rolls out huge VIP catalog merging verification IP from Cadence with VIP from Denali acquisition
Today, Cadence introduced a robust VIP catalog fortified with IP obtained from last year’s Denali acquisition. However, the resulting catalog reflects more than just IP accretion. It also reflects the diffusion of some key Denali VIP concepts into the entire … Continue reading
Semico reports that ASICS, ASSPs, SoCs, and core-based ICs comprise the fastest growing category in MOS logic chips
EDA360 Insider followers will not be surprised to hear that Semico’s latest blog entry on Semico Spin claims that “Special Purpose Logic”—consisting of ASICS, ASSPs, SoCs, and core-based ICs—is now the fastest growing category for MOS logic chips and has … Continue reading
As usual, Apple has broken new ground with the iPad and now it’s time for the competition to weigh in. One of the newest competitors is the Motorola Xoom tablet, which is based on the Nvidia Tegra 2 mobile application … Continue reading
The Accellera standards organization board has unanimously approved the Universal Verification Methodology (UVM) 1.0 as an industry standard for verification interoperability. Read all about it in Richard Goering’s Industry Insights blog.
Over the past couple of weeks, I’ve extracted bits of information about IP subsystems from Semico’s recent report on the topic. This blog post is my last of this series and it deals with one interesting tidbit lodged way in … Continue reading
Fully-Depleted SOI: Is it the light at the end of the nanometer Moore’s Law tunnel? Building a high-performance, low-power ARM processor core with 20nm FD-SOI
Last week, EDN’s Ron Wilson wrote an article that discusses a significant announcement about 20nm SOI IC fabrication from the SOI Consortium (consisting of ARM, GLOBALFOUNDRIES, IBM, STMicroelectronics, Soitec, and CEA-Leti). The announcement concerns the construction of a 30K-gate ARM … Continue reading
For the past couple of weeks, I’ve been writing about several aspects of Semico’s IP Subsystem report. (see “Are IP subsystems the next big IP category?”) The report’s premise is that the rise of IP Subsystems—IP blocks that deliver complete … Continue reading
Deconstructing EDA360: Paul McLellan writes about the evolution of SoC design methodology in the era of re-aggregation
I’ve written before about Part 1 of the article in EE Times written by EDA veterans Jim Hogan and Paul McLellan (The SoC is dead! Long live the SoC!). EE Times published Part II, attributed to Paul McLellan, on December … Continue reading
EETimes just posted an article written by European editor Peter Clarke with an interview of Malcolm Penn, founder of and principal analyst with Future Horizons. Penn notes that 4Q 2010 shows the first semiconductor fab capacity growth in six quarters … Continue reading
In a move characterized as “not a material financial matter,” FPGA vendor Altera has announced the purchase of Avalon Microelectronics, a Canadian vendor of FPGA-centric IP used to design optical networking equipment. Networking has long been a mainstay application for … Continue reading
The first time I met Charlie Cheng, he was CEO of processor IP startup Lexra. Now he’s CEO of memory IP vendor Kilopass. No surprise, Cheng thinks that IP is the future for semiconductor revenues in the US and he … Continue reading
An article published this week in EDN about LTE baseband modems perfectly underscores how software is becoming much more important in the development of advanced nanometer SoCs. The article was written by Pascal Herczog of Cognovo, and it details the … Continue reading
Normally, I don’t post responses to my blog discussions on LinkedIn Groups, but I think Nalini Patel’s comment on my recent blog entry about the IP Roundtable discussion at the Low-Power Engineering Community is worthy of its own blog entry. … Continue reading
Ed Sperling over at the Low-Power Engineering Community just published the transcripts of a fascinating discussion about IP with Ken Brock, senior staff product marketing manager for logic libraries in Synopsys’ Solutions Group; Kalar Rajendiran, senior director of marketing at … Continue reading
Over the Thanksgiving holidays David Murray, Duolog’s CTO, published a blog entry titled “Automation without abstraction is like a bicycle without pedals.” In this blog entry, Murray describes “automation” he’s seen that’s been used to stitch up IP blocks into … Continue reading
Bryon Moyer, Editor of IC Design and Verification Journal, just published an extensive article on EDA360 that you might want to read (A Few Rounds on EDA360). It’s a quick read and I think it’s interesting to see the ideas … Continue reading