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- A head-to-head comparison of the ARM Cortex-M4 and –M0 processor cores by Jack Ganssle
- Friday Video: SoC in tiny 500mg backpack transforms cockroach into radio-controlled exploration vehicle
- Friday Video: A different kind of fab with some very, very cool machines
- Friday Video: Get the latest skinny on the IPC-2581 open interchange standard for PCB design
- Smartphones: Where PCIe has not gone before—but will. Sooner rather than later.
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- A head-to-head comparison of the ARM Cortex-M4 and –M0 processor cores by Jack Ganssle
- 3-processor SoC for digital still cameras incorporates an ARM 1136J-S RISC processor core plus separate image and video processors
- Download a free PDF of the Mixed-signal Methodology Guide, Chapter 1: Design Trends and Challenges
- Where is the mainstream IC process technology today? 28nm? 40nm? 65nm?
- GLOBALFOUNDRIES’ 28nm process comes in three flavors. Which is right for you?
- Zowie! More than 50 x86 cores on the Intel Knights Corner Manycore Coprocessor
- Is there stuff you don’t know about SuperSpeed USB 3.0?
- SanDisk shows 128Gbit, 3-level cell NAND Flash memory chip at ISSCC. Is 20nm (or 19nm) here, so soon?
- 10 ways to get your EDA tools to run faster, smoother, and longer
- What effect does the ARM Cortex-M0 core have on mixed-signal microcontroller design?
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Category Archives: Low Power
Friday Video: Freescale pits Kinetis L microcontroller against parts from Microchip, TI, and Renesas. Guess who wins the low-power derby?
I’ve written a lot this week about the low-power Kinetis L microcontroller from Freescale, a low-power, mixed-signal IC design now shipping in alpha silicon. I have just found this new Freescale video, which was probably shot at this week’s Freescale … Continue reading
Earlier this month at DAC, ARM, NXP, and Cadence hosted a panel on mixed-signal design as it applies to microcontroller design. Richard Goering posted a great summary of the topics discussed at the panel, but I want to tease out … Continue reading
Mr. 3D IC—aka Herb Reiter—spoke to an attentive group of packaging experts about the state of 3D IC technical and business development today at a MEPTEC luncheon held at the “luxurious” Biltmore Hotel in cental Silicon Valley. I’ve written about … Continue reading
Next week (Monday, Tuesday, and Wednesday) you can get all of your EDA questions answered at the Cadence DAC demo suites. There are 78 demos over the three days covering the following EDA topics: Mixed-signal and low-power design RTL-to-GDSII design … Continue reading
Moore’s Law is not dead but the vital signs have clearly changed. That was the key message I heard from Dr. Subramanian Iyer, Fellow and Chief Technologist at the IBM Systems & Technology Group, during the GSA Silicon Summit held … Continue reading
“Once upon a time, you would complain if your cell phone didn’t work on one [battery] charge,” said Qi Wang—Cadence Technical Marketing Group Director for Low-Power Solutions—during his EDPS presentation in Monterey last week. “After Apple introduced the iPhone, your … Continue reading
Last week at the Electronic Design Process Symposium held in Monterey, EDA analyst Gary Smith put together a session on low-power design and he prefaced the other presentations with one of his own showing where he though the improvements in … Continue reading
Brian Bailey has just published an article on low-power design in the EE Life section of EETimes. (See “Power 101 – Power consumption”) Here is Bailey’s premise: “Power, in my opinion, has become a game changer, not just for hardware … Continue reading
There are more than 79,997 ways for your low-power design to fail. Want to learn how to avoid a nasty surprise? For free?
There are a range of low-power design approaches for ASIC design including: Clock Gating Multi-Voltage Power Shutoff Dynamic Voltage Body Bias Adaptive Voltage All of the above Used in combination, there are more than 80,000 possible low-power modes that all … Continue reading
[Friday Video] iFixit tears down an iPad 3 4G LTE using spudger, heat gun, and guitar picks. Finds new processor, more RAM, new battery, etc.
Those folks at iFixit stop at nearly nothing to be the first to tear apart shiny new toys like the new Apple iPad (the iPad formerly known as the iPad 3). They flew to Australia to get a new iPad … Continue reading
EDPS (April 5-6) in Monterey tackles “Low-Power with Performance” in SoC Design with a high-powered group of presenters including: Gary Smith, the EDA industry’s go-to analyst, who will discuss “Low-clock-speed computing” Ian Ferguson, Director of Server Systems and Ecosystem at … Continue reading
Last week at DVCon, Cadence sponsored a low-power-themed lunch with the promise “Earn Your Degree in the Low-Power Arts and Sciences.” The panel consisted of: Qi Wang, technical marketing group director, Cadence Ruggero Castagnetti, distinguished engineer, LSI Corp. Sushma Honnavara … Continue reading
All ASIC and SoC designs are low-power designs at or below the 45nm node. For that reason alone, the industry has seen the rise of power-intent descriptions to help SoC and Silicon Realization teams develop new chip designs. For the … Continue reading
This week in the Microprocessor Report, the Linley Group announced its Analysts’ Choice Award winners and declared the ARM big.LITTLE multicore IP architecture as the best processor IP of the year: “Designed to extend battery life by up to 70%, … Continue reading
Nvidia Tegra 3 based on five ARM Cortex-A9 cores is mobile processor of the year declares Microprocessor Report
This week in the Microprocessor Report, the Linley Group announced its Analysts’ Choice Award winners and declared the Nvidia Tegra 3 to be the top mobile processor announced in 2011. As published in the article announcing the winners: “Choosing the … Continue reading
The Santa Clara Valley (SCV) Chapter of the IEEE Solid State Circuits Society is hosting a 3-hour short course in low-power design a the end of this month. The course is divided into two parts: Fundamentals of low-power design and … Continue reading
This week, IBM and Micron apparently made a joint announcement (or perhaps just IBM made an announcement) regarding the manufacture of Micron’s Hybrid Memory Cube. There are varying reports and I cannot find the original statements on either company’s Web … Continue reading
Last week at the 9th International SoC Conference in Newport Beach, I moderated a 3D IC panel that did a great job of exploring today’s state of the art for 3D IC development. I will be blogging the presentations made … Continue reading
Last month, I wrote about the introduction of Ambarella’s new A7L SoC for controlling HD video and digital still cameras. (See “3-processor SoC for digital still cameras incorporates an ARM 1136J-S RISC processor core plus separate image and video processors”.) … Continue reading
Experimental , ultra-low-power 1.2V, 65nm SoC from ST and MIT operates at 82.5MHz (!) maximum, 540KHz at 0.54V
Last week, ST Microelectronics and MIT’s Microsystems Technology Laboratory announced the development of a low-power 65nm SoC that operates an on-chip microprocessor core at supply voltages as low as 0.54V and the on-chip SRAM with supply voltages as low as … Continue reading
One more process node click, from 45nm to 32nm, bumped the clock rate of the Ambarella A7L SoC’s on-chip ARM 1136J-S RISC processor core to 600MHz from 528MHz. But reading the press release, I get the impression that the real … Continue reading
Processor Wars: NVIDIA reveals a phantom fifth ARM Cortex-A9 processor core in Kal-El mobile processor IC. Guess why it’s there?
NVIDIA has extended the path to many-core design by publishing a White Paper that reveals the existence of a fifth ARM Cortex-A9 processor core in the company’s previously discussed Kal-El mobile processor. This fifth processor core implements what the company … Continue reading
I’ve been discussing Gregg Bartlett’s talk at this week’s Global Technology Conference and thought I’d focus this blog post on one graphic: As I mentioned in my last post, “GLOBALFOUNDRIES’ 28nm process comes in three flavors. Which is right for you?”, … Continue reading
Over the past week, I’ve published a 6-part series of blog posts based on the Xilinx White Paper describing how the company developed the low-power aspects of its Series-7 FPGA families. The lessons apply to any team developing ASICs and … Continue reading