Category Archives: Memory

Friday Video: A personal invitation to Memcon from Sanjay Srivastava

Posted on August 17, 2012 by sleibson2

Want to know why you need to be at Memcon this year? Here’s Denali Software founder Sanjay Srivastava to tell you why: Now go and sign up! It’s a free ticket and includes breakfast, lunch, and some goodies—not to mention … Continue reading →

Posted in Memory, Silicon Realization, SoC, SoC Realization, System Realization | Tagged , , , , , , , | Leave a comment

3D Thursday: ARM, HP, and SK hynix join Hybrid Memory Cube Consortium (HMCC)

Posted on June 28, 2012 by sleibson2

Add ARM, HP, and SK hynix to the growing list of companies in the Hybrid Memory Cube Consortium (HMCC). The three new members join the original founding companies, Micron and Samsung, along with Altera, IBM, Microsoft, Open-Silicon, and Xilinx plus … Continue reading →

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Moore’s Law: Wanted, Dead or Alive

Posted on May 14, 2012 by sleibson2

Moore’s Law is not dead but the vital signs have clearly changed. That was the key message I heard from Dr. Subramanian Iyer, Fellow and Chief Technologist at the IBM Systems & Technology Group, during the GSA Silicon Summit held … Continue reading →

Posted in 20nm, 28nm, 32nm, 40nm, 65nm, EDA360, IBM, Low Power, Memory, Multicore, Packaging, TSV | Tagged , , , , , , , | 2 Comments

Multicore, the Memory Wall, and Numerical Compression—FREE Webcast now available

Posted on May 1, 2012 by sleibson2

Last month I posted a review of Al Wegener’s terrific IEEE Computer Society presentation “Multicore, the Memory Wall, and Numerical Compression.” (See “Will your multicore SoC hit the memory wall? Will the memory wall hit your SoC? Does it matter?”) … Continue reading →

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3D Thursday: The low down on low-power CPU-memory connections from EDPS

Posted on April 18, 2012 by sleibson2

Earlier this month at EDPS, Marc Greenberg, Director of Product Marketing for the Cadence Design IP Group, said that Wide I/O SDRAM memory was going to drive the earliest adoption of 3D IC assembly techniques. Not simply because Wide I/O … Continue reading →

Posted in 2.5D, 3D, EDA360, Memory, Packaging, Silicon Realization, SoC, SoC Realization, System Realization, Wide I/O | Tagged , , | Leave a comment

Will your multicore SoC hit the memory wall? Will the memory wall hit your SoC? Does it matter? (Re Post)

Posted on April 16, 2012 by sleibson2

Multicore SoC and processor designs were our solution to the death of Dennard Scaling when IC process geometries dropped below 90nm, when processor speeds hit 3GHz, and when processor power consumption went off the charts. Since 2004, we’ve transformed Moore’s … Continue reading →

Posted in EDA360, Memory, Silicon Realization, SoC, SoC Realization, System Realization | Leave a comment

Friday Video: Now that we’ve replaced floppies with Flash memory, how will we ever do this?

Posted on March 22, 2012 by sleibson2

On Friday, you get entertainment as well as technology in the EDA360 Insider. For your viewing pleasure, here is an old PC with two 5.25-inch and two 3.25-inch floppy drives playing J.S. Bach’s “Toccata and Fugue in D Minor” on … Continue reading →

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Memcon 2012 call for presentation submissions

Posted on March 19, 2012 by sleibson2

Memcon 2012 will take place at the Santa Clara Convention Center in the heart of Silicon Valley on Tuesday, September 2012. This is the biggest conference in the world devoted to the use and manufacture of semiconductor memory (RAM, NAND … Continue reading →

Posted in EDA360, Memory, Silicon Realization, SoC, SoC Realization, System Realization | Tagged , , , , , , | Leave a comment

SanDisk shows 128Gbit, 3-level cell NAND Flash memory chip at ISSCC. Is 20nm (or 19nm) here, so soon?

Posted on February 28, 2012 by sleibson2

I’ve just posted a blog entry in the Denali Memory Report on an important NAND Flash memory announcement by SanDisk. Please check it out. http://j.mp/A6wAju

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The return of the Denali Memory Report !!!

Posted on January 5, 2012 by sleibson2

The Denali Memory Report covered events and trends in the semiconductor memory and storage industries for more than a decade. It has now returned as a blog (www.denalimemoryreport.com). There’s only one blog post so far, but I can assure you … Continue reading →

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3D Thursday: Let’s end 2011 with a high-performance DRAM memory stack design. How would you improve it?

Posted on December 28, 2011 by sleibson2

For the last 3D Thursday blog post of 2011in the EDA360 Insider, I thought I’d take a flight of fancy and try to put as many of this year’s 3D IC concepts as possible together to see what we might … Continue reading →

Posted in 2.5D, 3D, EDA360, Memory, SoC, SoC Realization, System Realization | Tagged , , , , , , | Leave a comment

3D Thursday: Hybrid Memory Cube—Does anyone know what’s happening with IBM and Micron?

Posted on December 1, 2011 by sleibson2

This week, IBM and Micron apparently made a joint announcement (or perhaps just IBM made an announcement) regarding the manufacture of Micron’s Hybrid Memory Cube. There are varying reports and I cannot find the original statements on either company’s Web … Continue reading →

Posted in EDA360, Low Power, Memory, SoC, SoC Realization, System Realization, TSV | Tagged , , , | Leave a comment

3D Thursday (early): Steve’s Improbable History of 3D ICs? Six decades of 3D electronic packaging

Posted on November 9, 2011 by sleibson2

Last week at the 9th International SoC Conference in Newport Beach, I moderated a 3D IC panel that did a great job of exploring today’s state of the art for 3D IC development. I will be blogging the presentations made … Continue reading →

Posted in 28nm, 3D, EDA360, Low Power, Memory, TSV | Tagged , , , , , , , , , , , | 1 Comment

3D Thursday: Hybrid Memory Cube—wide I/O only more so—gets an industry consortium

Posted on October 13, 2011 by sleibson2

Back in August, I wrote about the 3D SDRAM assembly called the Micron Hybrid Memory Cube (HMC, see “Want to know more about the Micron Hybrid Memory Cube (HMC)? How about its terabit/sec data rate?”) and I called it a … Continue reading →

Posted in 3D, EDA360, Memory, Samsung, SoC Realization | Tagged , , , , , , | Leave a comment

Master the secrets of system design using DDR4 SDRAM

Posted on October 4, 2011 by sleibson2

It is rare that you get to sit at the feet of a certified master and learn. If you’re interested in designing with DDR4 SDRAM, then this is your chance. On Tuesday, October 25, at ARM TechCon, Marc Greenberg will … Continue reading →

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New memory models support system design for next year’s introduction of Everspin STT MRAMs

Posted on October 3, 2011 by sleibson2

I’ve written a lot about magnetic RAM (MRAM) including some recent coverage of a terrific MRAM panel at the Flash Memory Summit. (See “The return of magnetic memory? A review of the MRAM panel at the Flash Memory Summit” and … Continue reading →

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3-processor SoC for digital still cameras incorporates an ARM 1136J-S RISC processor core plus separate image and video processors

Posted on September 27, 2011 by sleibson2

One more process node click, from 45nm to 32nm, bumped the clock rate of the Ambarella A7L SoC’s on-chip ARM 1136J-S RISC processor core to 600MHz from 528MHz. But reading the press release, I get the impression that the real … Continue reading →

Posted in ARM, EDA360, Firmware, Low Power, Memory, Silicon Realization, SoC Realization, System Realization | Tagged , , , | Leave a comment

What’s it take to design DDR4 into your next SoC? Newly released DFI 3.0 Spec opens the flood gates for DDR4 design

Posted on September 19, 2011 by sleibson2

DDR4 SDRAM probably won’t be appearing until 2013 and probably won’t become the mainstream SDRAM technology until 2015 (updated estimates from “Memory to processors: “Without me, you’re nothing.” DDR4 is on the way.”) but the new DFI 3.0 preliminary specification … Continue reading →

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3D Thursday: Raspberry Pi Foundation’s $25 ARM board boots Linux using stacked DRAM

Posted on August 25, 2011 by sleibson2

Although it’s not presented at a 3D story to the public, the Raspberry Pi Foundation’s $25 alpha board based on a 700MHz ARM 11 processor is very much 3D because there’s an SDRAM stacked on top of the processor. Why? … Continue reading →

Posted in 3D, EDA360, Firmware, Linux, Memory, Packaging, Silicon Realization | Tagged , | Leave a comment

JEDEC releases more details about DDR4 SDRAM spec. Want to know what they are?

Posted on August 23, 2011 by sleibson2

Although DDR3 memory is just ramping up in sales, JEDEC has been working on the next-generation DDR4 specification for faster SDRAM that consumes even less power. To achieve these goals, JEDEC announced yesterday that has specified the following key features … Continue reading →

Posted in EDA360, Memory, SoC Realization | Tagged , , , | 1 Comment

Flash Memory Summit: Top 10 things you need to know about NAND Flash

Posted on August 15, 2011 by sleibson2

An annual panel that now traditionally closes the Flash Memory Summit (held last week in Santa Clara, CA) is Andy Marken’s “Top 10 things you need to know about NAND Flash.” It’s a great way to sum up the events … Continue reading →

Posted in EDA360, Memory, Silicon Realization, SoC Realization, System Realization | Tagged , , , , | 1 Comment

Friday Video: What’s Next For Memory Designs In 2012? – from Agilent

Posted on August 5, 2011 by sleibson2

Agilent has created a 6-part video series titled “What’s Next For Memory Designs In 2012?” that’s well worth a look. There’s about 30 minutes of video total, chopped into 2-8 minute pieces that you’ll want to watch if you have any … Continue reading →

Posted in EDA360, Memory, Packaging, System Realization | Tagged , , , , | 1 Comment

Is the 1-chip PC looming in the future?

Posted on July 20, 2011 by sleibson2

The blog entry I wrote yesterday about the IHS iSuppli report on PCs and ARM processors set me on a thought path about PC design. (See “IHS iSuppli predicts that ARM CPUs will grab 25% of the PC market by … Continue reading →

Posted in ARM, EDA360, Memory, Silicon Realization, SoC Realization, System Realization | Tagged , , , , | Leave a comment

Jim Hogan details his views of SoC opportunities and again reveals his SoC Realization investment shopping list

Posted on May 12, 2011 by sleibson2

Jim Hogan gave the keynote at today’s EETimes Virtual SoC event and he presented a deep dive into the opportunities in semiconductor device development and the associated EDA opportunities from the perspective of an investor who makes his money building, … Continue reading →

Posted in EDA360, Firmware, IP, Low Power, Memory, Silicon Realization, SoC Realization, System Realization, Verification | Leave a comment

Urgent: You have only 24 hours to sign up for a free DDR4 Webinar including just-released info from the JEDEC committee

Posted on May 11, 2011 by sleibson2

I just heard from the Cadence memory interface guru himself, Marc Greenberg, about a DDR4 Webinar he’s giving tomorrow (Thursday) during the EETimes Virtual SoC event. Here’s what Marc wrote: “I am presenting a Webinar on DDR4 tomorrow (Thursday) at … Continue reading →

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