Category Archives: Silicon Realization

3D Thursday: Hella big conference on multi-die integration in the heart of Silicon Valley

There’s a strange little high-rise hotel called the Biltmore in the center of Silicon Valley at the intersection of the Montague Expressway and Highway 101. It’s going to be the site of this year’s “Roadmaps for Multi Die Integration” conference … Continue reading

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Would you like a guide to several new microcontrollers based on the ARM Cortex-M series of processor cores?

Alban Rampon has just published a guide to many new developments surrounding the ARM Cortex-M series of microcontroller cores. The guide includes a discussion of Freescale Kinetis L microcontrollers based on the ARM Cortex-M0+ core; discussions of microcontrollers based on … Continue reading

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3D Thursday: Produce cost-effective 2.5D and 3D devices. Attend the Known Good Die conference, November 15

Robert Patti, Chief Technical Officer and VP of Design Engineering at Tezzaron Semiconductor is the just-announced speaker at the Known Good Die conference being held on November 15 in Santa Clara, CA. His topic: Using Repair & Redundancy with KGD … Continue reading

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Where do semiconductor foundries come from?

Have you ever wondered how we got from a world solely occupied by semiconductor vendors with their own fabs to today’s hodgepodge of IDMs (independent device manufacturers, the new name for the old-style “semiconductor vendor”), fab-lite vendors, and fables vendors? … Continue reading

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3D Thursday: Intel Penwell SoC for mobile phones employs POP (package-on-package) LPDDR2 SDRAM to reduce power

Wednesday at the Hot Chips 24 conference, Rumi Zahir of Intel discussed the company’s Penwell SoC designed for cell phone handsets. The SoC is employed in the Medfield cellular handset design and it’s based on the Intel Atom x86 processor … Continue reading

Posted in 3D, EDA360, Packaging, Silicon Realization, SoC, SoC Realization, System Realization | Tagged , , , , , , , | 7 Comments

Zowie! More than 50 x86 cores on the Intel Knights Corner Manycore Coprocessor

Today at the Hot Chips 24 conference, George Chrysos discussed the Intel MIC (Many Integrated Core) architecture of the Knights Bridge chip, to be formally called the Intel Xeon Phi coprocessor. This chip runs Linux, but it’s designed to act … Continue reading

Posted in EDA360, Silicon Realization, SoC, SoC Realization, System Realization | Tagged , , , , , | 2 Comments

Paul McLellan on 20nm design

EDA analyst and SemiWiki writer Paul McLellan published an article on 20nm design last week. It’s based on the Cadence White Paper on the same topic. You can see Paul’s article here. The Cadence 20nm White Paper is here.

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Workshop on Analog and Mixed-Signal Design Automation: November 8 in Silicon Valley

A 1-day workshop on Analog and Mixed-Signal Design Automation will be held on November 8 in conjunction with ICCAD in Silicon Valley. It’s no secret that advanced-node process scaling makes all IC design more complex and more challenging—even more so … Continue reading

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Daniel Nenni at SemiWiki publishes a [very] brief history of the SoC

Daniel Nenni has just posted a very brief history of the SoC, with heavy emphasis on SoCs for mobile products. The emphasis is probably warranted because mobile designs really have driven SoC design for the past decade. One of the … Continue reading

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Friday Video: A personal invitation to Memcon from Sanjay Srivastava

Want to know why you need to be at Memcon this year? Here’s Denali Software founder Sanjay Srivastava to tell you why: Now go and sign up! It’s a free ticket and includes breakfast, lunch, and some goodies—not to mention … Continue reading

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Download a free PDF of the Mixed-signal Methodology Guide, Chapter 1: Design Trends and Challenges

A couple of days ago, I let you know that Cadence had just published a comprehensive book on mixed-signal SoC design and verification. The book’s title is the “Mixed-Signal Methodology Guide,” written by the top mixed-signal design experts from across … Continue reading

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Samsung Exynos 5 Dual mobile processor features two 1.7GHz ARM Cortex-A15 processors, a WQXGA display controller, and two LPDDR3 controllers to feed ‘em

This past weekend, the Web was abuzz with last week’s unveiling of Samsung’s Exynos 5 Dual mobile processor. This SoC features two 1.7GHz ARM Cortex-A15 processors rather than the previous Exynos generation Dual mobile processor that incorporated two 1.4GHz ARM … Continue reading

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New Mixed-Signal Methodology Guide provides design, verification and implementation methodologies for advanced mixed-signal designs

Cadence has just published the “Mixed-Signal Methodology Guide,” which provides an overview of design, verification and implementation methodologies for advanced mixed-signal designs based on recommendations from the book’s co-authors—top mixed-signal design experts from across the industry including authors from Boeing, … Continue reading

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Looking for an introductory Verilog book? How’s $24.95 sound?

Bob Zeidman, founder and president of Zeidman Consulting, has just published the third edition of his book “Introduction to Verilog.” It was first published a dozen years ago and is based on the Verilog seminars that Zeidman has given at … Continue reading

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Need to make an ARM Cortex-A9 processor core all it can be?

A new blog published today on the ARM Web site titled “How do you take an ARM POP up one more notch?” describes a very recent collaboration between ARM and Cadence to enhance the ARM POP IP, which helps any … Continue reading

Posted in 40nm, ARM, Cortex-A9, Silicon Realization, SoC, SoC Realization, TSMC | Tagged , , , , | Leave a comment

5-minute, 20nm Q&A. All you need to know in 5 minutes.

What are the key advantages of moving to 20nm? There are three primary reasons why we are seeing more system and semiconductor companies consider 20nm: performance, power, and area (PPA). Essentially, this is a “next-node” answer, which is still as … Continue reading

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Cavium “Thunders” approval of 64-bit ARM v8 processor cores for cloud and server apps

In an unusual press release, network processor vendor Cavium has revealed plans for Project Thunder,” which will develop a family of multi-core SoCs based on the 64-bit ARM v8 processor architecture. The processors will be full-custom cores based on the … Continue reading

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3D Thursday: Wide I/O and TSVs have a ripple effect on the DRAM controller. Who knew?

Currently, the JEDEC Wide I/O DRAM specification looks to be the biggest driving force behind the adoption of 3D IC assembly. The 512-bit data maw of a Wide I/O SDRAM provides high bandwidth with low power levels, both excellent arguments … Continue reading

Posted in 2.5D, 3D, DAC, EDA360, IP, Silicon Realization, SoC, SoC Realization, System Realization, TSV, Wide I/O | Tagged , , , , , | Leave a comment

3D Thursday: Will water cooling for 3D IC assemblies ever be practical?

Last week, Brian Bailey published an interview with Professor Madhavan Swaminathan who is the Director of the Interconnect and Packaging Center (IPC) at Georgia Tech in Atlanta. The topic of the interview was cooling of 3D IC devices. It’s no … Continue reading

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3D Thursday: Magnificent Max explains 3D IC in simple terms

If you’re looking for simplified explanations of technical topics, few people write them as well as Clive “Max” Maxfield. His simplified 3-page explanation of 3D IC assembly is here. (Note: Registration needed to go past page 1, unfortunately.)

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Can 1000 processors dance on the head of a pin? MIT’s Professor Srini Devadas hopes so

Veteran EDA industry watcher Peggy Aycinena visited MIT recently and spoke with Professor Srini Devadas about a manycore processor project called “Angstrom.” The purpose of the project is to develop massively parallel hardware—as in 1024 processors—to explore better ways of … Continue reading

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ARM, TSMC announce collaboration on FINfet-based ARM v8 processor core for sub-20nm SoC designs

Today, ARM and TSMC announced a multi-year deal to develop a 64-bit ARM v8 processor “beyond” the 20nm node using FINfets. The collaboration includes the ARMv8 architecture, ARM Artisan physical IP, and TSMC’s FinFET process technology. The target of this … Continue reading

Posted in 10nm, 14nm, 20nm, ARM, EDA360, Silicon Realization, SoC, SoC Realization | Tagged , , | Leave a comment

Friday Video: Luigi Capodieci, a fellow at GLOBALFOUNDRIES, talks 20nm and below, EUV, FINFETs, and the state of the foundry business

Be sure to watch this excellent 13-minute interview done by Mark LePedus starring Luigi Capodieci, a fellow with GLOBALFOUNDRIES, to get a close-up-and-personal look at the state of the foundry business (it’s not dying), 20nm design, EUV in the wings, … Continue reading

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3D Thursday: Micron stacks Phase-Change Memory and SDRAM

Yesterday, Micron announced volume production of a new memory device containing one 1Gbit PCM (phase-change memory) die and one 512Mbit LPDDR2 SDRAM die. The two die reside in the device package as stacked die, with wire-bonded interconnect. This is a … Continue reading

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Daniel Nenni in SemiWiki: 20nm is like mango beer. Surprisingly, “very good!!!”

Well this is a strange analogy that would never occur to me. Daniel Nenni in his new SemiWiki post compares the 20nm process node to—of all things—mango beer. He writes: “As it turns out, the mango beer is very good! … Continue reading

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