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- A head-to-head comparison of the ARM Cortex-M4 and –M0 processor cores by Jack Ganssle
- Friday Video: SoC in tiny 500mg backpack transforms cockroach into radio-controlled exploration vehicle
- Friday Video: A different kind of fab with some very, very cool machines
- Friday Video: Get the latest skinny on the IPC-2581 open interchange standard for PCB design
- Smartphones: Where PCIe has not gone before—but will. Sooner rather than later.
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- A head-to-head comparison of the ARM Cortex-M4 and –M0 processor cores by Jack Ganssle
- Ingenious architectural features allow ST to extract maximum performance from new microcontroller family based on ARM Cortex-M4. Cost: less than 6 bucks in 1000s
- 39 low-cost boards for embedded Linux application development starting with Raspberry Pi. Want the list?
- 3D Week: Wide I/O SDRAM, Network on Chip, Multicore, TSV, Asynchronous Logic—3D SoC stack from CEA-Leti and ST-Ericsson hits all the advanced notes. Can you say “Tour de Force”?
- Xilinx Vivado Design Suite brings SoC design style to advanced-node FPGA development
- 3D Thursday: More on the Xilinx Virtex 7 with 2.5D tiling. Wave of the future or stopgap measure?
- Want more information on the ARM Cortex-M0+ processor core?
- 3D Thursday (early): Steve’s Improbable History of 3D ICs? Six decades of 3D electronic packaging
- Friday Video: A blast from the past. Handifax 1000 promo video from mid 1990s shows how far we’ve come
- GLOBALFOUNDRIES’ 28nm process comes in three flavors. Which is right for you?
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Category Archives: Silicon Realization
3D Thursday: Want some real-world insight into 2.5D and 3D IC design and assembly? Read on to get the word from Tezzaron Semiconductor
Ann Steffora-Mutschler just published an interview with Robert Patti, chief technology officer at Tezzaron Semiconductor, that gives some terrific technical detail about 2.5D and 3D IC design and assembly. Patti provides some rare insight into today’s (as in right now) … Continue reading
Today I was reading this week’s issue of Time Magazine while eating lunch in my secret fish-and-chips restaurant at an undisclosed location in Milpitas, California when I chanced upon a fascinating article about RIM, maker of the BlackBerry. The article’s … Continue reading
Even if you are not currently considering 20nm design, you owe it to yourself to download and read a new 9-page White Paper titled “A Call to Action: How 20nm Will Change IC Design” to learn about some tectonic shifts … Continue reading
Thanks to this article from TechEye.Net, I was alerted to an extremely interesting roundtable discussion organized by the Kavli Foundation by three long-range nanotechnology research experts. The three experts are HP Research Fellow Stan Williams, director of the company’s Cognitive … Continue reading
Hear IBM’s Dr. Gary Patton on the future of silicon scaling…and beyond. (Audio from The Common Technology Platform Forum keynote)
Earlier this year, Dr. Gary Patton, Vice President of IBM’s Semiconductor Research and Development Center, spoke about the future of semiconductor scaling and beyond. It was a terrific keynote speech at the Common Platform Technology Forum and was similar to … Continue reading
Quoting a corporate press release, the Web site http://www.dpreview.com reports that Sony Corp intends to invest approximately 80 billion Yen through the end of March, 2014 to expand its capacity to manufacture “stacked silicon sensors,” which are 3D IC assemblies … Continue reading
Friday Video: EDA360 Insider talks HW/SW Codesign and Xilinx Zynq Dev Board with ChipEstimate.TV at DAC
I spent a few minutes with Sean O’Kane of ChipEstimate.TV at DAC earlier this month talking about system design, HW/SW codesign, and the new Avnet Dev Board for the Xilinx Zynq-7000 EPP. Here’s the video:
Friday Video: Freescale pits Kinetis L microcontroller against parts from Microchip, TI, and Renesas. Guess who wins the low-power derby?
I’ve written a lot this week about the low-power Kinetis L microcontroller from Freescale, a low-power, mixed-signal IC design now shipping in alpha silicon. I have just found this new Freescale video, which was probably shot at this week’s Freescale … Continue reading
Meaty new book on Mixed-Signal SoC Design, Verification and Implementation Methodology is nearly ready
Is your current SoC project a mixed-signal design? If not, chances are good that the next one will be. That’s because there’s been an evolution in SoC design from pure digital to analog/mixed-signal (AMS) designs over the past several years … Continue reading
There are two major reasons for reading this blog post: A 32-bit microcontroller that sells for as little as $0.49 in 10K quantities and consumes 50µA/MHz A $12.95 development board to be available late in September These are two of … Continue reading
This just out from DAC 2012: video interview with EDA bloggers Goering and Leibson on IP subsystems, 20nm, and more
Want to know what’s going to happen at DAC 2012? Oh, wait, that was a couple of weeks ago. Which is how long it took to get post this video of EDA bloggers Richard Goering and Steve Leibson from a … Continue reading
I conducted this video interview with Herb Reiter, “Mr. 3D IC” and president of eda2asic, the day after he spoke at a MEPTEC lunch in Silicon Valley—see “3D Thursday: The “King of 3D ICs” (Herb Reiter) speaks to his subjects—‘Learn … Continue reading
Mr. 3D IC—aka Herb Reiter—spoke to an attentive group of packaging experts about the state of 3D IC technical and business development today at a MEPTEC luncheon held at the “luxurious” Biltmore Hotel in cental Silicon Valley. I’ve written about … Continue reading
Yesterday I moderated a panel on 2(x)nm success at DAC and one of the panelists was Dr. Gary Patton, VP of IBM’s Semiconductor Research and Development Center in East Fishkill, NY. I’ve heard Dr. Patton speak before and he knows … Continue reading
Friday Video + 3D Thursday: Xilinx Virtex-7 H580T uses 3D assembly to merge 28Gbps xceivers, FPGA fabric
The first 3D part in the Xilinx Virtex-7 FPGA family—the 2000T—permitted the construction of a huge FPGA while sidestepping the yield issues of large 28nm die. Now, Xilinx has used 3D IC assembly to meld two FPGA logic slices and … Continue reading
Next week (Monday, Tuesday, and Wednesday) you can get all of your EDA questions answered at the Cadence DAC demo suites. There are 78 demos over the three days covering the following EDA topics: Mixed-signal and low-power design RTL-to-GDSII design … Continue reading
Yesterday, I wrote about a terrific discussion panel about the challenges of 20nm design at DAC. I am moderating the panel and there will be speakers from the Common Platform partners including IBM, Samsung, GLOBALFOUNDRIES (just confirmed!), and Cadence. (See … Continue reading
AMD’s new Trinity APU (Accelerated Processing Unit) for laptops/notebooks is a poster child for IP-centric SoC design
Yesterday, AMD introduced its second generation of A-series APUs (Accelerated Processing Units) that combine two to four Piledriver x86 microprocessor cores—each with 2Mbytes of L2 cache memory—with a Radeon 7000 GPU (Graphics Processing Unit), an HD Media Accelerator, a display … Continue reading
Want to know how to get to 20nm? Want to know why? Want breakfast at DAC on June 6? This is indeed your lucky day because you can get it all done at a special DAC breakfast panel titled “The … Continue reading
3D Thursday: Electronics Component and Technologies Conference in San Diego features several 3D learning opportunities. May 29-June 1.
The Electronics Component and Technologies Conference being held in San Diego on May 29-June 1 will provide you with several significant opportunities to come up to speed on 3D IC assembly and related topics including: Session 1 on 3D Interconnect … Continue reading
Layout Dependent Effects in Advanced Nodes: Boo! Are you scared yet? FREE DAC Seminar helps calm the nerves
You can change transistor threshold voltages on advanced-node designs just by placing them too near something else. (Scholarly paper with detailed analysis here.) You can solve this problem with overdesign but there are better ways. Layout-dependent effects and smart ways … Continue reading
Smart analog/mixed-signal IC designs are—er—smarter. Learn how to stuff a 32-bit ARM Cortex-M core into an AMS design at DAC. Lunch included
In these days of the SoC, one chip has to do it all. That means both analog and digital processing. Now you can get a first-hand look at how successful design teams have integrated ARM Cortex-M processor cores in their … Continue reading
At DAC, take the path to successful 20nm design. The same path leads to breakfast. Wednesday, June 6
If you’ve been following along—or even if you haven’t—Cadence held three 20nm Webinars last week. Perhaps you have to see it in person before you believe it. Fair enough. Here’s your chance to hear first-hand how you can develop high-yielding … Continue reading
The second of a series of three Cadence Webinars on 20nm design is now archived and available for viewing if you missed the live event. You can read about this Webinar in Richard Goering’s blog (“Cadence, Samsung Detail 20nm RTL-to-GDSII … Continue reading
Fujitsu adopts Cadence Chip Planning System for worldwide microcontroller design. Why? “It helps us build better chips faster.” Want one?
Fujitsu is one of the world’s top 10 microcontroller vendors. To stay competitive in this crowded, $15 billion market (2011 estimate by Databeans), a microcontroller vendor must freshen its microcontroller offerings at a very rapid pace and any boost in … Continue reading