Category Archives: SoC

What effect does the ARM Cortex-M0 core have on mixed-signal microcontroller design?

Earlier this month at DAC, ARM, NXP, and Cadence hosted a panel on mixed-signal design as it applies to microcontroller design. Richard Goering posted a great summary of the topics discussed at the panel, but I want to tease out … Continue reading

Posted in ARM, Cortex-M0, EDA360, Low Power, Mixed Signal, SoC, SoC Realization, System Realization | Tagged , , , , , | Leave a comment

Meaty new book on Mixed-Signal SoC Design, Verification and Implementation Methodology is nearly ready

Is your current SoC project a mixed-signal design? If not, chances are good that the next one will be. That’s because there’s been an evolution in SoC design from pure digital to analog/mixed-signal (AMS) designs over the past several years … Continue reading

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Freescale starts sampling $0.49 Kinetis L microcontrollers based on ARM Cortex-M0+ processor core

There are two major reasons for reading this blog post: A 32-bit microcontroller that sells for as little as $0.49 in 10K quantities and consumes 50µA/MHz A $12.95 development board to be available late in September These are two of … Continue reading

Posted in Cortex-M0, EDA360, Mixed Signal, Silicon Realization, SoC, SoC Realization, System Realization | Tagged , , , , | 4 Comments

This just out from DAC 2012: video interview with EDA bloggers Goering and Leibson on IP subsystems, 20nm, and more

Want to know what’s going to happen at DAC 2012? Oh, wait, that was a couple of weeks ago. Which is how long it took to get post this video of EDA bloggers Richard Goering and Steve Leibson from a … Continue reading

Posted in 20nm, 28nm, DAC, EDA360, Silicon Realization, SoC, SoC Realization, System Realization | Tagged , , , | Leave a comment

Can 2.5D IC assembly really reduce SoC software-development costs? Gabe Moretti thinks it can

Last week on the EDA Café Web site, EDA Editor and Industry Observer Gabe Moretti discussed my DAC blog post on Wally Rhines’ discussion of software’s role in the rising cost of SoC development. (See “Some chip-design reality from Mentor’s … Continue reading

Posted in 2.5D, 3D, EDA360, SoC, SoC Realization, System Realization | Tagged , , , , , , | Leave a comment

Friday Video: Mr. 3D IC, Herb Reiter, speaks about his start with 3D, where it is, where it’s going

I conducted this video interview with Herb Reiter, “Mr. 3D IC” and president of eda2asic, the day after he spoke at a MEPTEC lunch in Silicon Valley—see “3D Thursday: The “King of 3D ICs” (Herb Reiter) speaks to his subjects—‘Learn … Continue reading

Posted in 2.5D, 3D, EDA360, Silicon Realization, SoC, SoC Realization, System Realization | Tagged , , , , , , , , | Leave a comment

3D Thursday: The “King of 3D ICs” (Herb Reiter) speaks to his subjects—“Learn to work together”

Mr. 3D IC—aka Herb Reiter—spoke to an attentive group of packaging experts about the state of 3D IC technical and business development today at a MEPTEC luncheon held at the “luxurious” Biltmore Hotel in cental Silicon Valley. I’ve written about … Continue reading

Posted in 2.5D, 3D, DAC, EDA360, Low Power, Packaging, Silicon Realization, SoC, SoC Realization, System Realization, Wide I/O | Tagged , , , , , , , | 5 Comments

Heterogeneous SoC design gets its own foundation backed by heavy hitters. Good things sure to follow

I am an unabashed advocate of heterogeneous SoC design. Have been for decades. It’s a system-level design approach that lacks the elegance and academic symmetry of homogeneous processing in exchange for a more efficient, bare-metal, hard-core approach to system design … Continue reading

Posted in ARM, EDA360, ESL, Firmware, SoC, SoC Realization, System Realization | Tagged , , , , , , | 1 Comment

Some chip-design reality from Mentor’s Wally Rhines at last week’s annual DAC ESL panel

Last week at DAC, Mentor’s Chairman and CEO Wally Rhines chaired a panel on ESL but in his introduction, Wally spoke more about chip-design costs and associated software development. “The rapidly escalating cost of chip design has more to do … Continue reading

Posted in EDA360, ESL, SoC, SoC Realization, System Realization | Tagged , , , | 1 Comment

3D Thursday: My breakfast with IBM’s Gary Patton leads to a discussion of 20nm and 14nm IC design

Yesterday I moderated a panel on 2(x)nm success at DAC and one of the panelists was Dr. Gary Patton, VP of IBM’s Semiconductor Research and Development Center in East Fishkill, NY. I’ve heard Dr. Patton speak before and he knows … Continue reading

Posted in 14nm, 20nm, 28nm, Double Patterning, EDA360, EUV, Silicon Realization, SoC, SoC Realization | Tagged , , , , , , , | Leave a comment

Gary Smith proposes a 3-layer taxonomy for platform-based SoC design—Live from DAC 2012

EDA’s chief analyst Gary Smith is high on IP subsystems—big ones. Only Gary calls them platforms. Why is Smith so enthusiastic? Because, as he says, he was wrong last year in his estimates of how much it costs to develop … Continue reading

Posted in DAC, IP, SoC, SoC Realization, System Realization, Texas instruments | Tagged , , , , , , , , | Leave a comment

Friday Video + 3D Thursday: Xilinx Virtex-7 H580T uses 3D assembly to merge 28Gbps xceivers, FPGA fabric

The first 3D part in the Xilinx Virtex-7 FPGA family—the 2000T—permitted the construction of a huge FPGA while sidestepping the yield issues of large 28nm die. Now, Xilinx has used 3D IC assembly to meld two FPGA logic slices and … Continue reading

Posted in 2.5D, 28nm, 3D, EDA360, FPGA, Silicon Realization, SoC, SoC Realization, System Realization | Tagged , , , , | Leave a comment

DAC 2012: Get answers to all of your EDA questions at 78 Cadence demo suite slots

Next week (Monday, Tuesday, and Wednesday) you can get all of your EDA questions answered at the Cadence DAC demo suites. There are 78 demos over the three days covering the following EDA topics: Mixed-signal and low-power design RTL-to-GDSII design … Continue reading

Posted in DAC, EDA360, Low Power, Mixed Signal, pcb, Silicon Realization, SoC, SoC Realization, System Realization, TLM, Verification, VIP, Virtual Prototyping | Tagged , , , , , | Leave a comment

AMD’s new Trinity APU (Accelerated Processing Unit) for laptops/notebooks is a poster child for IP-centric SoC design

Yesterday, AMD introduced its second generation of A-series APUs (Accelerated Processing Units) that combine two to four Piledriver x86 microprocessor cores—each with 2Mbytes of L2 cache memory—with a Radeon 7000 GPU (Graphics Processing Unit), an HD Media Accelerator, a display … Continue reading

Posted in 32nm, EDA360, Silicon Realization, SoC, SoC Realization | Tagged , , , , , , , | Leave a comment

3D Thursday: Electronics Component and Technologies Conference in San Diego features several 3D learning opportunities. May 29-June 1.

The Electronics Component and Technologies Conference being held in San Diego on May 29-June 1 will provide you with several significant opportunities to come up to speed on 3D IC assembly and related topics including: Session 1 on 3D Interconnect … Continue reading

Posted in 2.5D, 3D, EDA360, Packaging, Silicon Realization, SoC, SoC Realization, System Realization | Tagged , , , | Leave a comment

Smart analog/mixed-signal IC designs are—er—smarter. Learn how to stuff a 32-bit ARM Cortex-M core into an AMS design at DAC. Lunch included

In these days of the SoC, one chip has to do it all. That means both analog and digital processing. Now you can get a first-hand look at how successful design teams have integrated ARM Cortex-M processor cores in their … Continue reading

Posted in ARM, Cortex-M0, Cortex-M4, DAC, Mixed Signal, Silicon Realization, SoC, SoC Realization | Tagged , , , , , | 2 Comments

At DAC, take the path to successful 20nm design. The same path leads to breakfast. Wednesday, June 6

If you’ve been following along—or even if you haven’t—Cadence held three 20nm Webinars last week. Perhaps you have to see it in person before you believe it. Fair enough. Here’s your chance to hear first-hand how you can develop high-yielding … Continue reading

Posted in 20nm, EDA360, IBM, Samsung, Silicon Realization, SoC, SoC Realization | Tagged , , , | Leave a comment

FREE Webinar on the Challenges of 20nm design. Second in a 3-part series from Cadence

The second of a series of three Cadence Webinars on 20nm design is now archived and available for viewing if you missed the live event. You can read about this Webinar in Richard Goering’s blog (“Cadence, Samsung Detail 20nm RTL-to-GDSII … Continue reading

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Does Soc verification leave you in a cold sweat? Read on…

Do you identify with this scenario: “I’m the verification lead on the biggest SoC our company has ever done. It’s taping out today and I’ve got that familiar sick feeling in my gut. When will the first undiscovered functional bugs … Continue reading

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Fujitsu adopts Cadence Chip Planning System for worldwide microcontroller design. Why? “It helps us build better chips faster.” Want one?

Fujitsu is one of the world’s top 10 microcontroller vendors. To stay competitive in this crowded, $15 billion market (2011 estimate by Databeans), a microcontroller vendor must freshen its microcontroller offerings at a very rapid pace and any boost in … Continue reading

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Four Significant EDA technologies of 2011 and what they mean to your IC design team

This week, Cadence celebrated the efforts of several developers who have created some very innovative technology during a private award ceremony. The reason I’m mentioning this internal event at all is because these celebrated technologies are already having a profoundly … Continue reading

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Friday Video: Short video demonstrates Samsung Exynos quad-core ARM Cortex-A9 mobile application processor against dual-core

This short 1.5-minute video gives you a high-level overview of the relative performance of a Samsung Exynos 4-core mobile applications processor based on the ARM Cortex-A9 processor core versus a dual-core version.

Posted in ARM, Cortex-A9, EDA360, Samsung, Silicon Realization, SoC, SoC Realization | Tagged , , , | Leave a comment

3D Thursday: GLOBALFOUNDRIES adds TSV capability for 28nm and 20nm die to Fab 8 in Saratoga County, New York

Customers’ clamor for 3D IC assembly capability and die with TSVs (through-silicon vias) has apparently gotten loud enough to cause a change of game plan for GLOBALFOUNDRIES, which announced today that it is spending “tens of millions of dollars” to … Continue reading

Posted in 20nm, 28nm, 3D, EDA360, Globalfoundries, Silicon Realization, SoC, SoC Realization, TSV | Tagged , , , , , , | Leave a comment

3D Thursday: Qualcomm’s Nick Yu says “3D DRAM stacking has started—it’s shipping in products”

Today’s GSA Silicon Summit held at the Computer History Museum in Mountain View, California included a talk on 3D IC assembly by Nick Yu, VP of Engineering, VLSI Engineering, at Qualcomm. Yu is in charge of Qualcomm’s technology roadmaps including … Continue reading

Posted in 2.5D, 3D, EDA360, Silicon Realization, SoC, SoC Realization, System Realization | Tagged , , , , , | Leave a comment

Three free Webinars answer your questions on 20nm SoC design. What questions do you have?

What can you reasonably expect to get from 20nm? What does it take to implement an ARM Cortex-A15 processor in 20nm? What might come between you and success at 20nm? How can you be more productive when creating 20nm designs? … Continue reading

Posted in 20nm, EDA360, Silicon Realization, SoC, SoC Realization, System Realization | Tagged , , , , | Leave a comment