Category Archives: SystemC

High-level synthesis, C versus assembly code, and Leibson’s Law

Years ago, when I was Editor-in-Chief of EDN Magazine, I coined (but did not name) Leibson’s Law: “It takes 10 years for any disruptive technology to become pervasive in the design community.” I was reminded of that observation while reading … Continue reading

Posted in Design Abstraction, EDA360, SoC, SoC Realization, System Realization, SystemC | Tagged , , , , | Leave a comment

System EDA tools attack today’s great bugaboo for SoC Realization: The Software Development Overhang

Today at the North American System C Users Group (NASCUG) meeting in San Jose, the Cadence Group Director of Product Marketing for System Development Frank Schirrmeister gave a really great overview and value proposition for extensive use of System Development … Continue reading

Posted in EDA360, FPGA prototyping, SoC, SoC Realization, System Realization, SystemC, TLM, Verification, VIP, Virtual Prototyping | Tagged , , , , , , , , | 1 Comment

IEEE Computer Society Lecture—Creating System-On-Chips: Mixing HW & SW Successfully

As soon as we started to incorporate processors on ASICs, thus instantly creating SoCs, hardware/software integration issues became fully intertwined with chip design. Today, we routinely put a dozen or more firmware-driven processing elements on our SoCs so the issues … Continue reading

Posted in EDA360, Silicon Realization, SoC, SoC Realization, System Realization, SystemC, TLM, Virtual Prototyping | Tagged , , , , | Leave a comment

Latest version of SystemC, IEEE 1666-2011, now supports TLM 2.0

Chocolate and peanut butter go together. So do SystemC and transaction-level modeling. Just not officially. Until now. Earlier this month, the IEEE Standards Board approved a revision to the IEEE 1666 SystemC standard to bring the widely used OSCI (Open … Continue reading

Posted in Design Abstraction, EDA360, SoC Realization, System Realization, SystemC, TLM | Tagged , , , , , , | Leave a comment

Free Webinar teaches you how to mix C, C++, SystemC, and SystemVerilog verification models within UVM—October 20

Our world is filled with mixed verification models and that fact isn’t going to change soon. If you would like to learn how to efficiently combine mixed verification models to work within the Accelera Universal Verification Methodology (UVM), then there’s … Continue reading

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A painless way to learn how to design and debug multicore ARM-based SoCs using SystemC and TLM 2.0

As SoCs become far more software-centric, and multicore SoCs even more so, Realization teams must prototype and debug their designs using virtual platforms before committing to the implementation phase or face the high risk of proceeding down the wrong architectural … Continue reading

Posted in ARM, EDA360, SoC Realization, System Realization, SystemC, TLM, Uncategorized, Virtual Prototyping | Tagged , , | Leave a comment