Search EDA360 Insider
Hey!!! Subscribe now to the EDA360 Insider!
-
Recent Posts
- A head-to-head comparison of the ARM Cortex-M4 and –M0 processor cores by Jack Ganssle
- Friday Video: SoC in tiny 500mg backpack transforms cockroach into radio-controlled exploration vehicle
- Friday Video: A different kind of fab with some very, very cool machines
- Friday Video: Get the latest skinny on the IPC-2581 open interchange standard for PCB design
- Smartphones: Where PCIe has not gone before—but will. Sooner rather than later.
EDA360 Tag Cloud
- 2.5D
- 3D
- 3D IC
- 20nm
- 28nm
- 32nm
- 40nm
- Agilent
- Altera
- AMD
- Analog
- Android
- Apple
- ARM
- ARM architecture
- ARM Cortex-A15
- ASIC
- Broadcom
- Cadence
- Canon
- Cortex
- Cortex-A15
- Cortex-M0
- DAC
- Dave Jones
- DDR3
- DDR4
- Double Patterning
- EDA
- EDPS
- Field-programmable gate array
- FinFET
- Flash
- Flash memory
- FPGA
- Freescale
- Freescale Semiconductor
- GlobalFoundries
- IBM
- Intel
- IP
- iPad
- iPhone
- JEDEC
- Jim Hogan
- Kinect
- Linux
- Low Power
- Lytro
- microcontroller
- Micron
- Microsoft
- Mixed Signal
- Multi-core processor
- Nvidia
- OrCAD
- pcb
- Printed circuit board
- Qualcomm
- Robot
- Samsung
- SDRAM
- Snapdragon
- SoC
- STMicroelectronics
- SystemC
- Texas Instruments
- TI
- TSMC
- USB
- verification
- video
- Wide I/O
- Xilinx
Top Posts
- A head-to-head comparison of the ARM Cortex-M4 and –M0 processor cores by Jack Ganssle
- Ingenious architectural features allow ST to extract maximum performance from new microcontroller family based on ARM Cortex-M4. Cost: less than 6 bucks in 1000s
- The DDR4 SDRAM spec and SoC design. What do we know now?
- About
- Power, Performance, Cost. FDSOI lets you pick any three. Want proof? How about an ARM Cortex-M0 processor core example?
- 3D Thursday: How Xilinx developed a 2.5D strategy for making the world’s largest FPGA and what the company might do next with the technology
- Download a free PDF of the Mixed-signal Methodology Guide, Chapter 1: Design Trends and Challenges
- Realizing the ARM Cortex-A15: What does the road to 2.5GHz look like?
- EETimes video of Xilinx Zync EPP shows that it takes six FPGAs to emulate one EPP
- Globalfoundries, LSI Corp, and Broadcom help Editorial Director Ed Sperling give the industry a low-power report card. How did we score?
Download the EDA360 Vision Paper here:
Category Archives: SystemC
High-level synthesis, C versus assembly code, and Leibson’s Law
Years ago, when I was Editor-in-Chief of EDN Magazine, I coined (but did not name) Leibson’s Law: “It takes 10 years for any disruptive technology to become pervasive in the design community.” I was reminded of that observation while reading … Continue reading
Posted in Design Abstraction, EDA360, SoC, SoC Realization, System Realization, SystemC
Tagged ASIC, High-level synthesis, LinkedIn, SoC, SystemC
Leave a comment
System EDA tools attack today’s great bugaboo for SoC Realization: The Software Development Overhang
Today at the North American System C Users Group (NASCUG) meeting in San Jose, the Cadence Group Director of Product Marketing for System Development Frank Schirrmeister gave a really great overview and value proposition for extensive use of System Development … Continue reading
IEEE Computer Society Lecture—Creating System-On-Chips: Mixing HW & SW Successfully
As soon as we started to incorporate processors on ASICs, thus instantly creating SoCs, hardware/software integration issues became fully intertwined with chip design. Today, we routinely put a dozen or more firmware-driven processing elements on our SoCs so the issues … Continue reading
Latest version of SystemC, IEEE 1666-2011, now supports TLM 2.0
Chocolate and peanut butter go together. So do SystemC and transaction-level modeling. Just not officially. Until now. Earlier this month, the IEEE Standards Board approved a revision to the IEEE 1666 SystemC standard to bring the widely used OSCI (Open … Continue reading
Posted in Design Abstraction, EDA360, SoC Realization, System Realization, SystemC, TLM
Tagged Accellera, EDA, IEEE 1666, OSCI, SoC Realization, SystemC, TLM
Leave a comment
Free Webinar teaches you how to mix C, C++, SystemC, and SystemVerilog verification models within UVM—October 20
Our world is filled with mixed verification models and that fact isn’t going to change soon. If you would like to learn how to efficiently combine mixed verification models to work within the Accelera Universal Verification Methodology (UVM), then there’s … Continue reading
Posted in System Realization, SystemC, UVM, Verification
Tagged Accelera, SystemC, SystemVerilog, TLM, UVM
Leave a comment
A painless way to learn how to design and debug multicore ARM-based SoCs using SystemC and TLM 2.0
As SoCs become far more software-centric, and multicore SoCs even more so, Realization teams must prototype and debug their designs using virtual platforms before committing to the implementation phase or face the high risk of proceeding down the wrong architectural … Continue reading
Posted in ARM, EDA360, SoC Realization, System Realization, SystemC, TLM, Uncategorized, Virtual Prototyping
Tagged A9, Cortex, M3
Leave a comment
