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Recent Posts
- A head-to-head comparison of the ARM Cortex-M4 and –M0 processor cores by Jack Ganssle
- Friday Video: SoC in tiny 500mg backpack transforms cockroach into radio-controlled exploration vehicle
- Friday Video: A different kind of fab with some very, very cool machines
- Friday Video: Get the latest skinny on the IPC-2581 open interchange standard for PCB design
- Smartphones: Where PCIe has not gone before—but will. Sooner rather than later.
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Top Posts
- A head-to-head comparison of the ARM Cortex-M4 and –M0 processor cores by Jack Ganssle
- 3D Thursday: Altera adds Avago MicroPOD optical interconnects to FPGA package to handle bidirectional 100Gbps Ethernet
- Qualcomm reveals more Snapdragon 4 SoC details in a White Paper. Want to know what’s inside?
- ARM drops Cortex-A7 core on unsuspecting market, devastates low-power SoC and application-processor landscapes. What’s it all mean?
- Download a free PDF of the Mixed-signal Methodology Guide, Chapter 1: Design Trends and Challenges
- How Skyera developed the 44Tbyte, enterprise-class Skyhawk SSD from the ground up. A System Realization story.
- EDA360 and the brand new Hewlett-Packard 15C Limited Edition RPN pocket scientific calculator
- Ingenious architectural features allow ST to extract maximum performance from new microcontroller family based on ARM Cortex-M4. Cost: less than 6 bucks in 1000s
- Who wants more technical detail on the Altera SoC FPGA? Altera says…you!
- By the numbers: 20nm (and 40nm, 32nm, 28nm, and 14nm) design to be discussed in technical detail at next week’s CDNLive! conference in Silicon Valley
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Category Archives: TSMC
Need to make an ARM Cortex-A9 processor core all it can be?
A new blog published today on the ARM Web site titled “How do you take an ARM POP up one more notch?” describes a very recent collaboration between ARM and Cadence to enhance the ARM POP IP, which helps any … Continue reading
Posted in 40nm, ARM, Cortex-A9, Silicon Realization, SoC, SoC Realization, TSMC
Tagged 40nm, ARM architecture, ARM Cortex-A9, process technology, TSMC
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Want details on the TSMC 20nm process technology?
Daniel Nenni has just published a great, short overview of the specifications for the TSMC 20nm process technology on his SemiWiki site. Nenni’s report hits the important benefits of the advanced process technology right at the beginning: 30% faster 1.9x … Continue reading
3D Thursday: Want to see a closeup of the TSMC 3D IC test vehicle?
Richard Goering just published a detailed blog post about the TSMC 2.5D/3D IC test vehicle, which TSMC is calling CoWoS (Chip on Wafer on Substrate) in his Industry Insights blog. This approach to 3D IC assembly bonds active silicon die … Continue reading
3D Thursday: Practical Approaches to 3-D IC—TSV/Silicon Interposer and Wide IO Implementation From People Who Have Been There, Done That
If you’re like me, you’ve heard more than enough theory about 3D IC assembly and you’re ready to get on with the main event and design something. Want to hear about 3D IC technology that works? Now? Then you will … Continue reading
Looking at 20nm design? Three free Webinars can help.
With the 20nm click on the process technology dial staring us in the face, you might be wanting some informative, experience-based help. Three free Webinars taking place on May 1, 2, and 3 will give you some extra oomph in … Continue reading
Posted in 20nm, EDA360, Silicon Realization, TSMC
Tagged 20nm, Cadence, Double Patterning, TSMC
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3D Thursday: TSMC’s 3D plans and the word on 3D from Xilinx, Nvidia, IMEC, and STATS ChipPAC
For another take on last month’s RTI 3D conference held in Burlingame, CA, see Dr. Phil Garrou’s blog on the ElectroIQ site. Click here. For previous EDA360 Insider coverage of this event, see “3D Week: Wide I/O SDRAM, Network on … Continue reading
Posted in 3D, EDA360, Silicon Realization, SoC Realization, System Realization, TSMC
Tagged Imec, Nvidia, STATS ChipPAC, TSMC, Xilinx
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Want to know the secrets of implementing an ARM Cortex-A15 in an advanced process node? Read on!
ARM and Cadence have just announced the tape out of the industry’s first 20nm design based on the ARM Cortex-A15 MPCore processor. The test chip targets TSMC’s 20nm process and it was jointly developed by engineers from ARM, TSMC, and … Continue reading
Posted in ARM, EDA360, Silicon Realization, SoC, SoC Realization, System Realization, TSMC
Tagged ARM architecture, ARM Cortex-A15, ARM Cortex-A15 MPCore, Texas Instruments, TSMC
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3D Thursday: IMEC prototypes 3D chip stack, finds some thermal surprises
Imec and several of its 3D integration partners (Globalfoundries, Intel, Micron, Panasonic, Samsung, TSMC, Fujitsu, Sony, Amkor, and Qualcomm) have fabricated a 3-chip 3D IC stack demonstration prototype with the intent of proving several assembly methods plus electrical characteristics and … Continue reading
Posted in 3D, Silicon Realization, SoC Realization, System Realization, TSMC, TSV
Tagged Amkor, Fujitsu, GlobalFoundries, Imec, Intel, Micron, Panasonic, Qualcomm, Samsung, Sony, TSMC
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Cadence collaboration produces TSMC Reference Flow 12.0 and Analog-Mixed-Signal (AMS) Reference Flow v2.0 for 28nm including ESL and 3D TSV DFT support
Today’s the first day of DAC and Cadence is sponsoring a 20nm development panel and lunch at the Omni Hotel adjacent to the San Diego Convention Center. At the same time, Cadence and TSMC have been cooperating on the TSMC … Continue reading
Posted in 3D, AMS, DAC, EDA360, imec, Silicon Realization, TSMC, TSV
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Cadence and TSMC collaborate on SoC IP development, produce complete USB IP package
Working together with TSMC under the TSMC Open Innovation Platform initiative, Cadence has just introduced a certified USB 2.0/3.0 PHY/PCS/controller design IP package to support the wildly popular, advanced USB interface ports for ongoing SoC development using advanced process nodes. TSMC … Continue reading
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