Category Archives: TSV

3D Thursday: Wide I/O and TSVs have a ripple effect on the DRAM controller. Who knew?

Posted on August 2, 2012 by sleibson2

Currently, the JEDEC Wide I/O DRAM specification looks to be the biggest driving force behind the adoption of 3D IC assembly. The 512-bit data maw of a Wide I/O SDRAM provides high bandwidth with low power levels, both excellent arguments … Continue reading →

Posted in 2.5D, 3D, DAC, EDA360, IP, Silicon Realization, SoC, SoC Realization, System Realization, TSV, Wide I/O | Tagged , , , , , | Leave a comment

Moore’s Law: Wanted, Dead or Alive

Posted on May 14, 2012 by sleibson2

Moore’s Law is not dead but the vital signs have clearly changed. That was the key message I heard from Dr. Subramanian Iyer, Fellow and Chief Technologist at the IBM Systems & Technology Group, during the GSA Silicon Summit held … Continue reading →

Posted in 20nm, 28nm, 32nm, 40nm, 65nm, EDA360, IBM, Low Power, Memory, Multicore, Packaging, TSV | Tagged , , , , , , , | 2 Comments

3D Thursday: GLOBALFOUNDRIES adds TSV capability for 28nm and 20nm die to Fab 8 in Saratoga County, New York

Posted on April 26, 2012 by sleibson2

Customers’ clamor for 3D IC assembly capability and die with TSVs (through-silicon vias) has apparently gotten loud enough to cause a change of game plan for GLOBALFOUNDRIES, which announced today that it is spending “tens of millions of dollars” to … Continue reading →

Posted in 20nm, 28nm, 3D, EDA360, Globalfoundries, Silicon Realization, SoC, SoC Realization, TSV | Tagged , , , , , , | Leave a comment

3D Thursday: Hybrid Memory Cube—Does anyone know what’s happening with IBM and Micron?

Posted on December 1, 2011 by sleibson2

This week, IBM and Micron apparently made a joint announcement (or perhaps just IBM made an announcement) regarding the manufacture of Micron’s Hybrid Memory Cube. There are varying reports and I cannot find the original statements on either company’s Web … Continue reading →

Posted in EDA360, Low Power, Memory, SoC, SoC Realization, System Realization, TSV | Tagged , , , | Leave a comment

3D Thursday: How Xilinx developed a 2.5D strategy for making the world’s largest FPGA and what the company might do next with the technology

Posted on November 16, 2011 by sleibson2

Two weeks ago, I moderated a 3D IC panel at the 9th International SoC Conference in Newport Beach, California. Last week, I wrote about the first two speakers. (See “3D Thursday: Where can you start with 3D?” and “3D Thursday: … Continue reading →

Posted in 2.5D, 28nm, 3D, 65nm, Silicon Realization, SoC, SoC Realization, TSV | Tagged , , , , | 2 Comments

3D Thursday (early): Steve’s Improbable History of 3D ICs? Six decades of 3D electronic packaging

Posted on November 9, 2011 by sleibson2

Last week at the 9th International SoC Conference in Newport Beach, I moderated a 3D IC panel that did a great job of exploring today’s state of the art for 3D IC development. I will be blogging the presentations made … Continue reading →

Posted in 28nm, 3D, EDA360, Low Power, Memory, TSV | Tagged , , , , , , , , , , , | 1 Comment

Generation-jumping 2.5D Xilinx Virtex-7 2000T FPGA delivers 1,954,560 logic cells using 6.8 BILLION transistors (PREVIEW!)

Posted on October 25, 2011 by sleibson2

Xilinx announced today that it is shipping Virtex-7 2000T FPGAs to customers. This is one monster FPGA. Its 6.8 billion transistors deliver 1,954,560 logic cells, 21.55 Mbits of distributed SRAM, 2160 DSP slices, 46,512Kbits of block RAM, four PCIe ports, … Continue reading →

Posted in 28nm, 3D, 65nm, EDA360, Silicon Realization, SoC, SoC Realization, System Realization, TSV | Tagged , , , , , | Leave a comment

Want to know more about the Micron Hybrid Memory Cube (HMC)? How about its terabit/sec data rate?

Posted on August 22, 2011 by sleibson2

Last week, I quoted Ann Steffora Mutschler’s article about the information that Micron has revealed about it’s 3D Hybrid Memory Cube. Now that I’ve got the paper Micron presented at last week’s Hot Chips 23 conference, I’d like to explain … Continue reading →

Posted in 3D, EDA360, Packaging, Silicon Realization, TSV | Tagged , , , , | 2 Comments

3D Thursday: Micron’s 3D Hybrid Memory Cube delivers more DRAM bandwidth at lower power and in a smaller form factor using TSVs

Posted on August 18, 2011 by sleibson2

Ann Steffora Mutschler’s interview with Scott Graham, general manager for Micron’s Hybrid Memory Cube (HMC) and Joe Jeddeloh, whose team developed the logic portion of the HMC alerted me to the existence of Micron’s new Hybrid Memory Cube, a 3D … Continue reading →

Posted in 3D, EDA360, Silicon Realization, SoC Realization, System Realization, TSV | Tagged | Leave a comment

3D Thursday: IMEC prototypes 3D chip stack, finds some thermal surprises

Posted on July 14, 2011 by sleibson2

Imec and several of its 3D integration partners (Globalfoundries, Intel, Micron, Panasonic, Samsung, TSMC, Fujitsu, Sony, Amkor, and Qualcomm) have fabricated a 3-chip 3D IC stack demonstration prototype with the intent of proving several assembly methods plus electrical characteristics and … Continue reading →

Posted in 3D, Silicon Realization, SoC Realization, System Realization, TSMC, TSV | Tagged , , , , , , , , , , | 1 Comment

Cadence collaboration produces TSMC Reference Flow 12.0 and Analog-Mixed-Signal (AMS) Reference Flow v2.0 for 28nm including ESL and 3D TSV DFT support

Posted on June 6, 2011 by sleibson2

Today’s the first day of DAC and Cadence is sponsoring a 20nm development panel and lunch at the Omni Hotel adjacent to the San Diego Convention Center. At the same time, Cadence and TSMC have been cooperating on the TSMC … Continue reading →

Posted in 3D, AMS, DAC, EDA360, imec, Silicon Realization, TSMC, TSV | Leave a comment