Search EDA360 Insider
- A head-to-head comparison of the ARM Cortex-M4 and –M0 processor cores by Jack Ganssle
- Friday Video: SoC in tiny 500mg backpack transforms cockroach into radio-controlled exploration vehicle
- Friday Video: A different kind of fab with some very, very cool machines
- Friday Video: Get the latest skinny on the IPC-2581 open interchange standard for PCB design
- Smartphones: Where PCIe has not gone before—but will. Sooner rather than later.
EDA360 Tag Cloud2.5D 3D 3D IC 20nm 28nm 32nm 40nm Agilent Altera AMD Analog Android Apple ARM ARM architecture ARM Cortex-A15 ASIC Broadcom Cadence Canon Cortex Cortex-A15 Cortex-M0 DAC Dave Jones DDR3 DDR4 Double Patterning EDA EDPS Field-programmable gate array FinFET Flash Flash memory FPGA Freescale Freescale Semiconductor GlobalFoundries Google IBM Intel IP iPad iPhone JEDEC Jim Hogan Kinect Linux Low Power Lytro microcontroller Micron Microsoft Mixed Signal Multi-core processor Nvidia OrCAD pcb Printed circuit board Qualcomm Robot Samsung SDRAM Snapdragon SoC STMicroelectronics SystemC Texas Instruments TI TSMC USB verification video Wide I/O Xilinx
- A head-to-head comparison of the ARM Cortex-M4 and –M0 processor cores by Jack Ganssle
- 3D Thursday: Altera adds Avago MicroPOD optical interconnects to FPGA package to handle bidirectional 100Gbps Ethernet
- 3D Thursday: 28nm design and 2.5D packaging saves Xilinx a ton of power. You can too even if you're not designing FPGAs!
- 3D Thursday (early): Steve’s Improbable History of 3D ICs? Six decades of 3D electronic packaging
- Friday Video: The Easter Egg in the Agilent InfiniiVision 3000 X-Series DSO
- 3D Thursday: More on the Xilinx Virtex 7 with 2.5D tiling. Wave of the future or stopgap measure?
- The DDR4 SDRAM spec and SoC design. What do we know now?
- 3D Thursday: Intel and FinFETs (Tri-Gate transistors)—a different kind of 3D
Download the EDA360 Vision Paper here:
Category Archives: Verification
A couple of days ago, I let you know that Cadence had just published a comprehensive book on mixed-signal SoC design and verification. The book’s title is the “Mixed-Signal Methodology Guide,” written by the top mixed-signal design experts from across … Continue reading
Less than two days left to sign up for free PCIe and NVMe verification training Webinar from Cadence
On June 25, Cadence and EETimes Education and Training are sponsoring a training Webinar covering verification flows for SoC designs with PCIe and/or NVMe interfaces. The Webinar will cover: Verification pitfalls of the PCIe and NVMe interface protocols Best practices … Continue reading
Even if you are not currently considering 20nm design, you owe it to yourself to download and read a new 9-page White Paper titled “A Call to Action: How 20nm Will Change IC Design” to learn about some tectonic shifts … Continue reading
You have only hours to sign up for a free Webinar on using the Cadence Incisive Metric Center taking place this coming Wednesday at noon (US Eastern Time). “What’s that?” you might ask. The Incisive Metrics Center simplifies the way … Continue reading
Next week (Monday, Tuesday, and Wednesday) you can get all of your EDA questions answered at the Cadence DAC demo suites. There are 78 demos over the three days covering the following EDA topics: Mixed-signal and low-power design RTL-to-GDSII design … Continue reading
Do you identify with this scenario: “I’m the verification lead on the biggest SoC our company has ever done. It’s taping out today and I’ve got that familiar sick feeling in my gut. When will the first undiscovered functional bugs … Continue reading
Analog blocks are usually verified at the block level many things still go wrong with connectivity and control of the analog circuit at the SoC level. It’s not enough to integrate these analog blocks into digital simulations; you need to … Continue reading
Do you need to improve verification performance for advanced-node SoCs? Learn how on May 14 in Munich.
The state space of a chip grows exponentially every 24 months. That’s the verification corollary to Moore’s Law. Verification engineers tackle the problem with faster simulation but that’s no longer enough. The complete verification cycle includes compilation/elaboration; RTL/gate/SV/e/SystemC mixed-mode simulation; … Continue reading
Last week, I attended an all-day Agilent seminar on a variety of interface standards including USB 3.0. As it turns out, there was a lot I didn’t know about USB 3.0. Perhaps you did not know some of these things … Continue reading
Last month, Richard Goering wrote an excellent blog post on “Best Practices for Selecting and Using Verification IP (VIP).” In this blog post, Richard listed ten questions you should make sure you can answer when selecting commercial VIP. The ten … Continue reading
You’ve seen robotic Rubik’s cube solvers before—even in EDA360 Insider. (For example, see “Friday Video: Multicore, ARM-powered CubeStormer II solved Rubik’s Cube puzzle in world-beating 4.762 seconds”). Well, Cadence once again had its robotic Rubik’s Cube solver powered by Incisive … Continue reading
System EDA tools attack today’s great bugaboo for SoC Realization: The Software Development Overhang
Today at the North American System C Users Group (NASCUG) meeting in San Jose, the Cadence Group Director of Product Marketing for System Development Frank Schirrmeister gave a really great overview and value proposition for extensive use of System Development … Continue reading
The growth of standards-based interfaces and the rapid advance in the state of the art for SoC design have created a real need for pro-quality verification IP (VIP). One interesting facet of VIP development is its parallel evolution with design … Continue reading
This fascinating article about the evolution of Twinkies snack cakes by former supermarket exec Dick Schindler should give every System Realization team something to chew on (pun intended). Schindler’s list of changes made to the Twinkies formulation to reduce costs … Continue reading
As the size and complexity of mixed-signal designs have grown, so has the verification task. Designers face the challenging task of verifying complex power, performance, and functionality specifications as well as validating analog and digital interactions over a broad range … Continue reading
Verification expert Kathleen Meade has authored a methodology for applying UVM runtime phases that appears in the second edition of the Cadence UVM Book. On December 7, Kathleen will present a free verification Webinar covering the following topics: Basics of … Continue reading
Scoreboarding “app” for Formal verification tools allows anyone to get exhaustive verification results—even on datapaths
If you think you know what Formal verification is all about, you are probably wrong. There’s a free webinar coming up on November 17 that will blow out the walls on your boxed-in thinking about Formal. The Webinar is about … Continue reading
When is it OK to stop verifying your design? Free Webinar will tell you how to know when you’ve done enough
Verification takes a big chunk out of your development budget and one of the most difficult questions to answer about verification is: “When and how will I know if we’re done?” One word: “Metrics.” If you want to know when … Continue reading
Free Webinar teaches you how to mix C, C++, SystemC, and SystemVerilog verification models within UVM—October 20
Our world is filled with mixed verification models and that fact isn’t going to change soon. If you would like to learn how to efficiently combine mixed verification models to work within the Accelera Universal Verification Methodology (UVM), then there’s … Continue reading
Friday Video: What does it take to get to 20nm? Samsung’s VP of Foundry North America Ana Hunter explains
Samsung has been pushing IC process technology about as hard as any company in the business. It’s foundry business is operating at 65nm and 32/28nm with a 20nm process node in development. (See my recent blog “Samsung 20nm test chip … Continue reading
Want a shortcut to automating assertion generation for simulation, formal verification, and emulation flows?
Assertion-based verification (ABV) helps ASIC and SoC design and verification teams using simulation, formal analysis, and emulation methodologies accelerate verification signoff by enhancing the RTL and test specifications to include assertions and functional coverage properties, which are logic statements that … Continue reading
A new report from In-Stat notes “a dramatic increase for HDMI in portable consumer devices, including HD camcorders and digital still cameras. In addition, on the PC side, HDMI’s share of mobile PCs, graphics cards, and PC monitors continued to … Continue reading
Everyone knows that there’s a standard set of interfaces that PC chipsets must support: the DDR standard of the day (today it’s likely to be DDR3, tomorrow DDR4), PCIe, Ethernet (10/100/1G), USB (today it’s 2.0, tomorrow 3.0), and HDMI to … Continue reading
Friday Video: Rubik’s Cube puzzle solved with Lego Mindstorms robot and… Cadence Incisive Formal Verifier???
Normally, you don’t use a formal verification tool to solve puzzles like Rubik’s Cube and you also don’t normally connect the verification tool to a robot. No, things are usually more cut and dried than that. However, there’s nothing that … Continue reading