Category Archives: Verification

How can you be sure DDR2, DDR3, and DDR4 SDRAMs will work properly in your system?

LeCroy introduced an upgrade to its Kibra 380 DDR3 SDRAM protocol analyzer today. The analyzer’s probes plug in series with the DDR3 SDRAM modules and the analyzer can identify more than 65 JEDEC command protocol and timing violations in real … Continue reading

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Open-Silicon’s Naveed Sherwani speaks about the verification crisis in SoC design with unusual clarity

Last month at DAC, Richard Goering interviewed Open-Silicon CEO Naveed Sherwani for ChipEstimate.tv. The main topic was Open-Silicon’s new “on time or on us” chip delivery program but the last few minutes of the 11-minute video interview cover the very … Continue reading

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Detailed analysis of the Cadence PCIe Gen 3 IP and VIP launch from SemiWiki’s Eric Esteve

A bit of analysis and a little history goes a long way to fleshing out the product announcement of Cadence’s PCIe Gen 3 IP and VIP offerings. This just-published analysis by SemiWiki’s Eric Esteve provides both.

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The DDR4 SDRAM spec and SoC design. What do we know now?

DDR4 SDRAM is coming. JEDEC may not have released the final spec yet but Samsung made the first DDR4 memory chip announcement in January of this year—a 2133MHz device built with a 30nm process technology—and Hynix followed suit in April … Continue reading

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Jim Hogan details his views of SoC opportunities and again reveals his SoC Realization investment shopping list

Jim Hogan gave the keynote at today’s EETimes Virtual SoC event and he presented a deep dive into the opportunities in semiconductor device development and the associated EDA opportunities from the perspective of an investor who makes his money building, … Continue reading

Posted in EDA360, Firmware, IP, Low Power, Memory, Silicon Realization, SoC Realization, System Realization, Verification | Leave a comment

What’s driving 3D IC design? Do 2D EDA tools need a total overhaul to support 3D design?

The Electronic Design Process Symposium (EDPS) held last week in Monterey devoted most of Friday to a discussion of 3D design. I’ll be devoting several EDA360 Insider blog entries to this important topic. Today’s entry summarizes the presentation by Rahul … Continue reading

Posted in 3D, Design Abstraction, Design Convergence, Design Intent, EDA360, Low Power, Packaging, Silicon Realization, SoC Realization, System Realization, Verification | Leave a comment

Wide I/O. Don’t leave your SoC without it

Today, Cadence introduced three critical IP components that support the Wide I/O memory interface. These components include a configurable memory controller, a Wide I/O PHY, and appropriate verification IP. You can read more about this announcement in Richard Goering’s “Industry … Continue reading

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SemiWiki’s Eric Esteve: VIP says “Without me, you’re nothing!”

Eric Esteve just published an article over at SemiWiki titled “IP would be nothing without VIP…” that provides a good background of VIP and some analysis of the market. Check it out here.

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EETimes video of Xilinx Zync EPP shows that it takes six FPGAs to emulate one EPP

A pointer on http://www.design-reuse.com led to some excellent videos from the Embedded World event in Germany last week. The videos are from the Xilinx booth at Embedded World and show the pre-silicon emulation boards Xilinx has developed for the Zynq … Continue reading

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How many people does it take to design an SoC? Perspectives from Ron Collett and the EDA360 Insider

The man who’s probably done as much primary research on EDA and best ASIC design practices as anyone in the business, Ron Collett, just published an article in EE Times titled “Optimal team sizes for chip projects.” In his article, … Continue reading

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Want 40% better SoC performance with 30% less power consumption? Mentor’s Wally Rhines says look to System Realization (without using those words) in his DVcon 2011 keynote

Mentor CEO Wally Rhines stood in front of the DVcon 2011 audience yesterday, delivering his keynote speech and said “The entire population of India will need to become verification engineers” if current trends continue. A shocking assertion perhaps, but one … Continue reading

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Cadence rolls out huge VIP catalog merging verification IP from Cadence with VIP from Denali acquisition

Today, Cadence introduced a robust VIP catalog fortified with IP obtained from last year’s Denali acquisition. However, the resulting catalog reflects more than just IP accretion. It also reflects the diffusion of some key Denali VIP concepts into the entire … Continue reading

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Asynchronous FIFO design disaster forces silicon respin. A cautionary SoC design tale from the trenches.

Dealing with asynchronous clocks is like trick-or-treating on a dark and stormy night in a spooky neighborhood: the environment is full of hidden demons and monsters. Today’s blog post from Cadence’s Tom Anderson (The Tale of the Silicon Re-Spin and … Continue reading

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