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Recent Posts
- A head-to-head comparison of the ARM Cortex-M4 and –M0 processor cores by Jack Ganssle
- Friday Video: SoC in tiny 500mg backpack transforms cockroach into radio-controlled exploration vehicle
- Friday Video: A different kind of fab with some very, very cool machines
- Friday Video: Get the latest skinny on the IPC-2581 open interchange standard for PCB design
- Smartphones: Where PCIe has not gone before—but will. Sooner rather than later.
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Top Posts
- A head-to-head comparison of the ARM Cortex-M4 and –M0 processor cores by Jack Ganssle
- 3D Thursday: Altera adds Avago MicroPOD optical interconnects to FPGA package to handle bidirectional 100Gbps Ethernet
- Qualcomm reveals more Snapdragon 4 SoC details in a White Paper. Want to know what’s inside?
- ARM drops Cortex-A7 core on unsuspecting market, devastates low-power SoC and application-processor landscapes. What’s it all mean?
- Download a free PDF of the Mixed-signal Methodology Guide, Chapter 1: Design Trends and Challenges
- How Skyera developed the 44Tbyte, enterprise-class Skyhawk SSD from the ground up. A System Realization story.
- EDA360 and the brand new Hewlett-Packard 15C Limited Edition RPN pocket scientific calculator
- Ingenious architectural features allow ST to extract maximum performance from new microcontroller family based on ARM Cortex-M4. Cost: less than 6 bucks in 1000s
- Who wants more technical detail on the Altera SoC FPGA? Altera says…you!
- By the numbers: 20nm (and 40nm, 32nm, 28nm, and 14nm) design to be discussed in technical detail at next week’s CDNLive! conference in Silicon Valley
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Category Archives: VIP
Less than two days left to sign up for free PCIe and NVMe verification training Webinar from Cadence
On June 25, Cadence and EETimes Education and Training are sponsoring a training Webinar covering verification flows for SoC designs with PCIe and/or NVMe interfaces. The Webinar will cover: Verification pitfalls of the PCIe and NVMe interface protocols Best practices … Continue reading
Posted in EDA360, SoC Realization, System Realization, Verification, VIP
Tagged NVMe, PCIe, verification, VIP, Webinar
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DAC 2012: Get answers to all of your EDA questions at 78 Cadence demo suite slots
Next week (Monday, Tuesday, and Wednesday) you can get all of your EDA questions answered at the Cadence DAC demo suites. There are 78 demos over the three days covering the following EDA topics: Mixed-signal and low-power design RTL-to-GDSII design … Continue reading
Posted in DAC, EDA360, Low Power, Mixed Signal, pcb, Silicon Realization, SoC, SoC Realization, System Realization, TLM, Verification, VIP, Virtual Prototyping
Tagged DAC, EDA, IC design, pcb, synthesis, verification
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Four Significant EDA technologies of 2011 and what they mean to your IC design team
This week, Cadence celebrated the efforts of several developers who have created some very innovative technology during a private award ceremony. The reason I’m mentioning this internal event at all is because these celebrated technologies are already having a profoundly … Continue reading
LeCroy’s “Basic” Edition Advisor T3 USB 3.0 Protocol Analyzer costs $2995
The latest USB buzz has notebook computers with SuperSpeed USB 3.0 ports becoming common by mid year, thanks to last week’s announcement of USB 3.0 protocol support in Intel’s 7-Series chipset for current-generation Intel Core processors and next-generation Ivy Bridge … Continue reading
Posted in EDA360, SoC, SoC Realization, System Realization, USB, VIP
Tagged Intel, Ivy Bridge, Sandy Bridge, SuperSpeed, USB, USB 3.0
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10 questions to ask your verification IP (VIP) supplier
Last month, Richard Goering wrote an excellent blog post on “Best Practices for Selecting and Using Verification IP (VIP).” In this blog post, Richard listed ten questions you should make sure you can answer when selecting commercial VIP. The ten … Continue reading
Posted in EDA360, SoC, SoC Realization, System Realization, Verification, VIP
Tagged verification, VIP
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System EDA tools attack today’s great bugaboo for SoC Realization: The Software Development Overhang
Today at the North American System C Users Group (NASCUG) meeting in San Jose, the Cadence Group Director of Product Marketing for System Development Frank Schirrmeister gave a really great overview and value proposition for extensive use of System Development … Continue reading
Do you know all of the essential aspects of VIP to make a good make/buy decision?
The growth of standards-based interfaces and the rapid advance in the state of the art for SoC design have created a real need for pro-quality verification IP (VIP). One interesting facet of VIP development is its parallel evolution with design … Continue reading
Posted in EDA360, Silicon Realization, SoC, SoC Realization, System Realization, Verification, VIP
Tagged SoC, verification, VIP
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