Category Archives: Virtual Prototyping

DAC 2012: Get answers to all of your EDA questions at 78 Cadence demo suite slots

Posted on May 29, 2012 by sleibson2

Next week (Monday, Tuesday, and Wednesday) you can get all of your EDA questions answered at the Cadence DAC demo suites. There are 78 demos over the three days covering the following EDA topics: Mixed-signal and low-power design RTL-to-GDSII design … Continue reading →

Posted in DAC, EDA360, Low Power, Mixed Signal, pcb, Silicon Realization, SoC, SoC Realization, System Realization, TLM, Verification, VIP, Virtual Prototyping | Tagged , , , , , | Leave a comment

Four Significant EDA technologies of 2011 and what they mean to your IC design team

Posted on May 3, 2012 by sleibson2

This week, Cadence celebrated the efforts of several developers who have created some very innovative technology during a private award ceremony. The reason I’m mentioning this internal event at all is because these celebrated technologies are already having a profoundly … Continue reading →

Posted in EDA360, Silicon Realization, SoC, TLM, VIP, Virtual Prototyping | Tagged , , , , | Leave a comment

Hardware/Software Codesign: Pink elephants on parade?

Posted on February 29, 2012 by sleibson2

As part of this week’s DVCon event being held in Silicon Valley, the EDAC Emerging Companies Committee sponsored a really intense and well-attended evening panel on hardware/software codesign. The effervescent Paul McLellan moderated the panel. (If you’ve not read his book, … Continue reading →

Posted in EDA360, Firmware, SoC, SoC Realization, System Realization, Virtual Prototyping | Tagged , , , , , , , | Leave a comment

System EDA tools attack today’s great bugaboo for SoC Realization: The Software Development Overhang

Posted on February 27, 2012 by sleibson2

Today at the North American System C Users Group (NASCUG) meeting in San Jose, the Cadence Group Director of Product Marketing for System Development Frank Schirrmeister gave a really great overview and value proposition for extensive use of System Development … Continue reading →

Posted in EDA360, FPGA prototyping, SoC, SoC Realization, System Realization, SystemC, TLM, Verification, VIP, Virtual Prototyping | Tagged , , , , , , , , | 1 Comment

IEEE Computer Society Lecture—Creating System-On-Chips: Mixing HW & SW Successfully

Posted on February 16, 2012 by sleibson2

As soon as we started to incorporate processors on ASICs, thus instantly creating SoCs, hardware/software integration issues became fully intertwined with chip design. Today, we routinely put a dozen or more firmware-driven processing elements on our SoCs so the issues … Continue reading →

Posted in EDA360, Silicon Realization, SoC, SoC Realization, System Realization, SystemC, TLM, Virtual Prototyping | Tagged , , , , | Leave a comment

Real Case History: Virtual Platform shrinks embedded software debug and troubleshooting time from days to minutes

Posted on February 8, 2012 by sleibson2

This new blog by Jason Andrews (an Architect at Cadence who specializes in hardware/software coverification and embedded software) recounts the experience of one software engineer, stymied by a problem running on a real prototype, who switched to a Virtual Platform … Continue reading →

Posted in EDA360, System Realization, Virtual Prototyping | Tagged , , | Leave a comment

How do virtual prototyping, emulation, and FPGA prototyping differ? Answers from Frank Schirrmeister

Posted on January 30, 2012 by sleibson2

Trying to suss out the differences among virtual prototyping, emulation, and FPGA prototyping? Richard Goering recently interviewed Frank Schirrmeister, group director of product marketing for the Cadence System and Software Realization Group, in Goering’s Industry Insights blog and the interview … Continue reading →

Posted in EDA360, System Realization, Virtual Prototyping | Tagged , | Leave a comment

Friday Video: Want a demo of the Xilinx Zynq 7000 EPP virtual platform?

Posted on December 15, 2011 by sleibson2

Don’t get the whole virtual platform thing as it applies to the new Xilinx Zynq 7000 EPP? Here’s the concise explanation and a demo in three and a half minutes from ChipEstimate.com.

Posted in EDA360, SoC Realization, System Realization, Virtual Prototyping | Tagged , | Leave a comment

Want to start writing code for the two ARM Cortex-A9 processors on the Xilinx Zynq-7000 EPP right now? Virtual Platform makes it possible

Posted on October 26, 2011 by sleibson2

As of today, you can start to develop application software for the Xilinx Zynq-7000 family of Extensible Processing Platforms (EPP) using a virtual prototyping platform announced today and jointly developed by Xilinx and Cadence. The virtual platform provides an accurate … Continue reading →

Posted in Apps, ARM, Cortex-A9, EDA360, FPGA prototyping, SoC Realization, System Realization, TLM, Virtual Prototyping | Tagged , , , , , | Leave a comment

A painless way to learn how to design and debug multicore ARM-based SoCs using SystemC and TLM 2.0

Posted on October 5, 2011 by sleibson2

As SoCs become far more software-centric, and multicore SoCs even more so, Realization teams must prototype and debug their designs using virtual platforms before committing to the implementation phase or face the high risk of proceeding down the wrong architectural … Continue reading →

Posted in ARM, EDA360, SoC Realization, System Realization, SystemC, TLM, Uncategorized, Virtual Prototyping | Tagged , , | Leave a comment