Category Archives: Wide I/O

3D Thursday: Wide I/O and TSVs have a ripple effect on the DRAM controller. Who knew?

Currently, the JEDEC Wide I/O DRAM specification looks to be the biggest driving force behind the adoption of 3D IC assembly. The 512-bit data maw of a Wide I/O SDRAM provides high bandwidth with low power levels, both excellent arguments … Continue reading

Posted in 2.5D, 3D, DAC, EDA360, IP, Silicon Realization, SoC, SoC Realization, System Realization, TSV, Wide I/O | Tagged , , , , , | Leave a comment

3D Thursday: The “King of 3D ICs” (Herb Reiter) speaks to his subjects—“Learn to work together”

Mr. 3D IC—aka Herb Reiter—spoke to an attentive group of packaging experts about the state of 3D IC technical and business development today at a MEPTEC luncheon held at the “luxurious” Biltmore Hotel in cental Silicon Valley. I’ve written about … Continue reading

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Posted in 2.5D, 3D, DAC, EDA360, Low Power, Packaging, Silicon Realization, SoC, SoC Realization, System Realization, Wide I/O | Tagged , , , , , , , | 5 Comments

3D Thursday: The low down on low-power CPU-memory connections from EDPS

Earlier this month at EDPS, Marc Greenberg, Director of Product Marketing for the Cadence Design IP Group, said that Wide I/O SDRAM memory was going to drive the earliest adoption of 3D IC assembly techniques. Not simply because Wide I/O … Continue reading

Posted in 2.5D, 3D, EDA360, Memory, Packaging, Silicon Realization, SoC, SoC Realization, System Realization, Wide I/O | Tagged , , | Leave a comment

3D Thursday: Is Wide I/O SDRAM free for the end user???

A recent email from Marc Greenberg, Director of Product Marketing for the Cadence Design IP Group, suggested that Wide I/O used in a 3D stack is free for the end user. In other words, there’s no incremental cost in the … Continue reading

Posted in 3D, EDA360, Silicon Realization, SoC, SoC Realization, System Realization, Wide I/O | Tagged , , , , | Leave a comment

3D Thursday: CEA-Leti launches Open 3D IC assembly partnership program

ElectroIQ reports that CEA-Leti in Grenoble has just launched an Open 3D IC program to permit companies more open access to the 3D IC assembly technologies developed at the research center. Last December, CEA-Leti and ST-Ericsson made a joint presentation … Continue reading

Posted in 2.5D, 3D, EDA360, Silicon Realization, SoC, SoC Realization, System Realization, Wide I/O | Tagged , , , , , , | Leave a comment

3D Thursday: Count Renesas in with the 3D IC poker game, says Nikkei Electronics

Last week, Masahide Kimura at Nikkei Electronics in Japan published an article titled “Renesas to Commercialize TSV Technology for Wide I/O DRAM-compatible Mobile SoCs” that clearly puts Renesas in the middle of the industry’s 3D IC efforts. Reading between the … Continue reading

Posted in 3D, EDA360, Silicon Realization, SoC, SoC Realization, System Realization, Wide I/O | Tagged , , , , | Leave a comment

3D Week: JEDEC Wide I/O Memory spec cleared for use

According to Ken Shoemaker, Vice-Chair of the JEDEC 42.6 Low Power Memories committee, the Wide I/O specification has been finalized and approved by the directors. It will be published shortly. Participants in the effort included representatives from Elpida, Hynix, Micron, … Continue reading

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