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- Friday Video: Get the latest skinny on the IPC-2581 open interchange standard for PCB design
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Top Posts
- A head-to-head comparison of the ARM Cortex-M4 and –M0 processor cores by Jack Ganssle
- EDA360 and the brand new Hewlett-Packard 15C Limited Edition RPN pocket scientific calculator
- 10 ways to get your EDA tools to run faster, smoother, and longer
- Qualcomm reveals more Snapdragon 4 SoC details in a White Paper. Want to know what’s inside?
- Friday Video: Ready for a little mobile phone teardown archaeology? Dave Jones compares state of the art in 1994 (Motorola) with an evolved 2000 (Nokia)
- 20nm design: What have we learned so far?
- The DDR4 SDRAM spec and SoC design. What do we know now?
- 3D Week: Wide I/O SDRAM, Network on Chip, Multicore, TSV, Asynchronous Logic—3D SoC stack from CEA-Leti and ST-Ericsson hits all the advanced notes. Can you say “Tour de Force”?
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Tag Archives: 14nm
Scaling the peaks to look at the 14nm cliff, Part 2: Tom Beckley from Cadence explains how we’re getting to 20nm and then on to 14nm and 10nm
This week at the ISQED Symposium in Silicon Valley, Tom Beckley who is the Senior VP of R&D for Custom IC and Signoff at Cadence opened the conference with a keynote covering the industry’s challenges and progress at 20nm and … Continue reading
Posted in 10nm, 14nm, 20nm, 28nm, Design Abstraction, Design Intent, DFM, Double Patterning, EDA360, IBM, Silicon Realization
Tagged 10nm, 14nm, 20nm, 28nm, extraction, FinFET, ISQED, layout, parasitic
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Scaling the 20nm peaks to look at the 14nm cliff, Part 1: Tom Beckley from Cadence maps the challenges of advanced node design at ISQED
Yesterday at the ISQED Symposium in Silicon Valley, Tom Beckley who is the Senior VP of R&D for Custom IC and Signoff at Cadence opened the conference with a keynote that lays out the challenges for IC designers tackling advanced … Continue reading
Posted in 14nm, 20nm, EDA360, Silicon Realization, SoC, SoC Realization
Tagged 14nm, 20nm, design rules, ISQED
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Want to know what’s going to happen at 20nm, 14nm, and beyond? A few answers from Frank Leu of Cadence
Last week at the Global Technology Forum held at the Santa Clara Convention Center in Silicon Valley, Cadence VP of R&D Frank Leu discussed the things we’ve learned about 20nm IC manufacturing, what we are learning about 14nm, and where … Continue reading
Posted in 14nm, 20nm, 28nm, EDA360, Globalfoundries, Samsung, Silicon Realization, SoC, SoC Realization, System Realization
Tagged 14nm, 20nm, 28nm, Cadence, IBM, In-Design, Samsung
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By the numbers: 20nm (and 40nm, 32nm, 28nm, and 14nm) design to be discussed in technical detail at next week’s CDNLive! conference in Silicon Valley
There’s still time to register for CDNLive!, which is being held on March 13 and 14 at the Doubletree Hotel in San Jose, California so let me give you a few numbers to whet your appetite: 40nm, 32nm, 28nm, 20nm, … Continue reading
Posted in 14nm, 20nm, 28nm, 32nm, 40nm, CDNLive!, EDA360, Silicon Realization, SoC, SoC Realization, System Realization
Tagged 14nm, 20nm, 28nm, 32nm, 40nm, CDNLive!, Double Patterning, Doubletree, GlobalFoundries, IBM, Samsung
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Friday Video: Common Platform Technology Forum reveals program agenda, rolls into Silicon Valley on March 14
The Common Platform partners are IBM, Samsung, and GLOBALFOUNDRIES and their annual Technology Forum rolls into Silicon Valley on March 14, so you have a couple of weeks to sign up. This short video from ChipEstimate.com gives you a good … Continue reading
Posted in 14nm, 20nm, 28nm
Tagged 14nm, 20nm, 28nm, Common Platform, GlobalFoundries, IBM, Samsung
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GLOBALFOUNDRIES talks FinFETs, EUV, 14nm, ETSOI. Any other bleeding-edge chipmaking terms you wanted to hear?
Near the end of his Global Technology Conference presentation last week, Senior VP of Technology and R&D Gregg Bartlett jumped to the future—namely 2014 to 2015. By then, GLOBALFOUNDRIES plans to be implementing the second production phase for its 20nm … Continue reading
Posted in EDA360, Globalfoundries, Silicon Realization
Tagged 14nm, 20nm, ETSOI, EUV, FinFET
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