Search EDA360 Insider
Hey!!! Subscribe now to the EDA360 Insider!
-
Recent Posts
- A head-to-head comparison of the ARM Cortex-M4 and –M0 processor cores by Jack Ganssle
- Friday Video: SoC in tiny 500mg backpack transforms cockroach into radio-controlled exploration vehicle
- Friday Video: A different kind of fab with some very, very cool machines
- Friday Video: Get the latest skinny on the IPC-2581 open interchange standard for PCB design
- Smartphones: Where PCIe has not gone before—but will. Sooner rather than later.
EDA360 Tag Cloud
- 2.5D
- 3D
- 3D IC
- 20nm
- 28nm
- 32nm
- 40nm
- Agilent
- Altera
- AMD
- Analog
- Android
- Apple
- ARM
- ARM architecture
- ARM Cortex-A15
- ASIC
- Broadcom
- Cadence
- Canon
- Cortex
- Cortex-A15
- Cortex-M0
- DAC
- Dave Jones
- DDR3
- DDR4
- Double Patterning
- EDA
- EDPS
- Field-programmable gate array
- FinFET
- Flash
- Flash memory
- FPGA
- Freescale
- Freescale Semiconductor
- GlobalFoundries
- IBM
- Intel
- IP
- iPad
- iPhone
- JEDEC
- Jim Hogan
- Kinect
- Linux
- Low Power
- Lytro
- microcontroller
- Micron
- Microsoft
- Mixed Signal
- Multi-core processor
- Nvidia
- OrCAD
- pcb
- Printed circuit board
- Qualcomm
- Robot
- Samsung
- SDRAM
- Snapdragon
- SoC
- STMicroelectronics
- SystemC
- Texas Instruments
- TI
- TSMC
- USB
- verification
- video
- Wide I/O
- Xilinx
Top Posts
- A head-to-head comparison of the ARM Cortex-M4 and –M0 processor cores by Jack Ganssle
- Ingenious architectural features allow ST to extract maximum performance from new microcontroller family based on ARM Cortex-M4. Cost: less than 6 bucks in 1000s
- EDA360 and the brand new Hewlett-Packard 15C Limited Edition RPN pocket scientific calculator
- RTOS pioneer Jim Ready discusses the intersection between embedded design and EDA
- EMA Design Automation announces FootprintGen—an app for Cadence Allegro and OrCAD PCB design tools that cuts the time needed to design PCB footprint models for new components
Download the EDA360 Vision Paper here:
Tag Archives: 2000T
3D Thursday: Is 2.5D IC assembly “buzz-worthy”?
I’ve written several times about the Xilinx Virtex-7 2000T FPGA that uses 2.5D IC assembly techniques to form four FPGA die into one FPGA package with two million logic cells. (See “3D Thursday: Generation-jumping 2.5D Xilinx Virtex-7 2000T FPGA delivers … Continue reading
Posted in 2.5D, 3D, Silicon Realization, SoC, SoC Realization
Tagged 2.5D, 2000T, 3D, Virtex 7, Xilinx
Leave a comment
3D Thursday: How Xilinx developed a 2.5D strategy for making the world’s largest FPGA and what the company might do next with the technology
Two weeks ago, I moderated a 3D IC panel at the 9th International SoC Conference in Newport Beach, California. Last week, I wrote about the first two speakers. (See “3D Thursday: Where can you start with 3D?” and “3D Thursday: … Continue reading
Posted in 2.5D, 28nm, 3D, 65nm, Silicon Realization, SoC, SoC Realization, TSV
Tagged 2.5D, 2000T, FPGA, SerDes, Xilinx
2 Comments
