Tag Archives: 28Gbps

Can 2.5D IC assembly really reduce SoC software-development costs? Gabe Moretti thinks it can

Last week on the EDA Café Web site, EDA Editor and Industry Observer Gabe Moretti discussed my DAC blog post on Wally Rhines’ discussion of software’s role in the rising cost of SoC development. (See “Some chip-design reality from Mentor’s … Continue reading

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Friday Video + 3D Thursday: Xilinx Virtex-7 H580T uses 3D assembly to merge 28Gbps xceivers, FPGA fabric

The first 3D part in the Xilinx Virtex-7 FPGA family—the 2000T—permitted the construction of a huge FPGA while sidestepping the yield issues of large 28nm die. Now, Xilinx has used 3D IC assembly to meld two FPGA logic slices and … Continue reading

Posted in 2.5D, 28nm, 3D, EDA360, FPGA, Silicon Realization, SoC, SoC Realization, System Realization | Tagged , , , , | Leave a comment

Amazing Friday Video: Xilinx GTZ SerDes transceivers pump 26Gbps/channel through Luxtera silicon photonics module

Setup for this video is pretty complicated so bear with me. The following video shows a Xilinx test chip with “7 Series GTX” transceivers pumping 26Gbps data over four channels through a stand-alone Luxtera “silicon optics” multichannel transceiver module. The … Continue reading

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