Tag Archives: Accelera

Free Webinar teaches you how to mix C, C++, SystemC, and SystemVerilog verification models within UVM—October 20

Our world is filled with mixed verification models and that fact isn’t going to change soon. If you would like to learn how to efficiently combine mixed verification models to work within the Accelera Universal Verification Methodology (UVM), then there’s … Continue reading


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OSCI and Accelera merger: And now the rest of the story courtesy of Stan Krolikoski

Accelera and OSCI (the SystemC standardization guys) announced their intent to merge this last week. Interoperability standards at multiple levels are important, so this is indeed an important announcement. Stan Krolikoski, Group Director for EDA/IP Standards & Interoperability at Cadence, … Continue reading

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EDA360, verification, UVM, and the future of EDA standards

Adam Sherilog Sherer, the Cadence Incisive Product Management Director, just published a blog about his experience in calling on several existing customers to discuss UVM (The Universal Verification Methodology being developed under Accelera’s banner). (“We Want UVM 1.0! When Do … Continue reading

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