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Top Posts
- A head-to-head comparison of the ARM Cortex-M4 and –M0 processor cores by Jack Ganssle
- Where is the mainstream IC process technology today? 28nm? 40nm? 65nm?
- EDA360 and the brand new Hewlett-Packard 15C Limited Edition RPN pocket scientific calculator
- Ingenious architectural features allow ST to extract maximum performance from new microcontroller family based on ARM Cortex-M4. Cost: less than 6 bucks in 1000s
- 3-processor SoC for digital still cameras incorporates an ARM 1136J-S RISC processor core plus separate image and video processors
- EMA Design Automation announces FootprintGen—an app for Cadence Allegro and OrCAD PCB design tools that cuts the time needed to design PCB footprint models for new components
- 3D Thursday: 28nm design and 2.5D packaging saves Xilinx a ton of power. You can too even if you're not designing FPGAs!
- Clock Concurrent Optimization: The Primer to the Primer—OR—Want to overcome some major functional hurdles to Silicon Realization and save a lot of power on your SoC at the same time?
- 39 low-cost boards for embedded Linux application development starting with Raspberry Pi. Want the list?
- Friday Video: Want the basics of PCB design in 45 minutes? Dave Jones delivers yet again with a free tutorial.
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Tag Archives: ASSP
Semico reports that ASICS, ASSPs, SoCs, and core-based ICs comprise the fastest growing category in MOS logic chips
EDA360 Insider followers will not be surprised to hear that Semico’s latest blog entry on Semico Spin claims that “Special Purpose Logic”—consisting of ASICS, ASSPs, SoCs, and core-based ICs—is now the fastest growing category for MOS logic chips and has … Continue reading
