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Recent Posts
- A head-to-head comparison of the ARM Cortex-M4 and –M0 processor cores by Jack Ganssle
- Friday Video: SoC in tiny 500mg backpack transforms cockroach into radio-controlled exploration vehicle
- Friday Video: A different kind of fab with some very, very cool machines
- Friday Video: Get the latest skinny on the IPC-2581 open interchange standard for PCB design
- Smartphones: Where PCIe has not gone before—but will. Sooner rather than later.
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Top Posts
- A head-to-head comparison of the ARM Cortex-M4 and –M0 processor cores by Jack Ganssle
- Power, Performance, Cost. FDSOI lets you pick any three. Want proof? How about an ARM Cortex-M0 processor core example?
- Friday Video: Learn the fundamentals of PCB design in 47 minutes, and enjoy it
- Intel says Moore’s Law alive and well and living at 32nm
- My workbench from 1978 highlighted in EETimes as one of engineering’s messiest desks
- Ingenious architectural features allow ST to extract maximum performance from new microcontroller family based on ARM Cortex-M4. Cost: less than 6 bucks in 1000s
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Tag Archives: Atrenta
3D Thursday: Some unexpected implications of IP subsystems coupled with 3D IC assembly
A new “Experts at the Table” conversation on the Semiconductor Manufacturing and Design Community (SMD) site about IP Subsystems among Kevin Meyer, vice president of design enablement strategy and alliances at GlobalFoundries; Steve Roddy, vice president of marketing at Tensilica; … Continue reading
Posted in 3D, EDA360
Tagged 3D IC, Atrenta, GlobalFoundries, IP Subsystems, Tensilica
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FREE DAC 2012 Exhibit 3-day passes. Limited quantity. Time-limited offer. Get ‘em NOW!
Want to go see the latest EDA offerings on the DAC exhibit floor but you (or your boss) can’t spring for the cash? Bummer. Atrenta, Cadence, and Springsoft feel your pain and once more, the three amigos have partnered to … Continue reading
Friday Video: Atrenta joins the Cadence System Realization Alliance. Customers win
Atrenta announced this week just before ARM TechCon 2011 that it has joined the Cadence System Realization Alliance. The first result of this agreement is to ensure seamless operation of the Atrenta Spyglass platform with the Cadence C-to-Silicon Compiler. Atrenta … Continue reading
