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Recent Posts
- A head-to-head comparison of the ARM Cortex-M4 and –M0 processor cores by Jack Ganssle
- Friday Video: SoC in tiny 500mg backpack transforms cockroach into radio-controlled exploration vehicle
- Friday Video: A different kind of fab with some very, very cool machines
- Friday Video: Get the latest skinny on the IPC-2581 open interchange standard for PCB design
- Smartphones: Where PCIe has not gone before—but will. Sooner rather than later.
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Top Posts
- A head-to-head comparison of the ARM Cortex-M4 and –M0 processor cores by Jack Ganssle
- Generation-jumping 2.5D Xilinx Virtex-7 2000T FPGA delivers 1,954,560 logic cells using 6.8 BILLION transistors (PREVIEW!)
- Friday Video + 3D Thursday: Xilinx Virtex-7 H580T uses 3D assembly to merge 28Gbps xceivers, FPGA fabric
- Download a free PDF of the Mixed-signal Methodology Guide, Chapter 1: Design Trends and Challenges
- Between ASIC and microcontroller: It’s all about System Realization
- Intel’s Knut Grimsrud explains how to get another 20x improvement in SSD performance
- Learn to use AI in design work after a great slice of Costco pizza. The talk is free. Pizza: $2
- 3D Thursday: Generation-jumping 2.5D Xilinx Virtex-7 2000T FPGA delivers 1,954,560 logic cells using 6.8 BILLION transistors (UPDATED!)
- 3D Thursday: Intel and FinFETs (Tri-Gate transistors)—a different kind of 3D
- Microprocessor Report publishes extremely interesting comparison of STMicroelectronics SPEAr-1300 and Xilinx Zynq ARM-based, dual core application processors
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Tag Archives: Brian Bailey
3D Thursday: Will water cooling for 3D IC assemblies ever be practical?
Last week, Brian Bailey published an interview with Professor Madhavan Swaminathan who is the Director of the Interconnect and Packaging Center (IPC) at Georgia Tech in Atlanta. The topic of the interview was cooling of 3D IC devices. It’s no … Continue reading
Posted in 2.5D, 3D, EDA360, Silicon Realization, SoC, SoC Realization, System Realization
Tagged 2.5D, 3D, Aquasar, Brian Bailey, FLOPS, IBM, Integrated circuit, SuperMUC, Water cooling
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Power is everything in design today. Believe it?
Brian Bailey has just published an article on low-power design in the EE Life section of EETimes. (See “Power 101 – Power consumption”) Here is Bailey’s premise: “Power, in my opinion, has become a game changer, not just for hardware … Continue reading
Posted in Low Power, Silicon Realization, SoC, SoC Realization, System Realization
Tagged Brian Bailey, EE Times, Jan Rabaey, Low Power
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Brian Bailey asks if hardware/software co-design is a myth or reality, then answers the question
Brian Bailey is a well-known consultant in the EDA industry and he’s just published a short but pithy blog on EETimes examining the state of the art in hardware/software co-design. Bailey does something I really admire in this blog. He … Continue reading
Posted in EDA360, Firmware, System Realization
Tagged Brian Bailey, co-design, codesign, hardware/software co-design
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