Tag Archives: Clock gating

Clock Concurrent Optimization: The Primer to the Primer—OR—Want to overcome some major functional hurdles to Silicon Realization and save a lot of power on your SoC at the same time?

Cadence has just announced the acquisition of Azuro, a Silicon Realization EDA company specializing in physical optimization, especially as it applies to clock trees. Azuro offers a 20-page White Paper on its Web site that discusses its technology, called Clock … Continue reading

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