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Recent Posts
- A head-to-head comparison of the ARM Cortex-M4 and –M0 processor cores by Jack Ganssle
- Friday Video: SoC in tiny 500mg backpack transforms cockroach into radio-controlled exploration vehicle
- Friday Video: A different kind of fab with some very, very cool machines
- Friday Video: Get the latest skinny on the IPC-2581 open interchange standard for PCB design
- Smartphones: Where PCIe has not gone before—but will. Sooner rather than later.
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Top Posts
- A head-to-head comparison of the ARM Cortex-M4 and –M0 processor cores by Jack Ganssle
- Where is the mainstream IC process technology today? 28nm? 40nm? 65nm?
- EDA360 and the brand new Hewlett-Packard 15C Limited Edition RPN pocket scientific calculator
- Ingenious architectural features allow ST to extract maximum performance from new microcontroller family based on ARM Cortex-M4. Cost: less than 6 bucks in 1000s
- 3-processor SoC for digital still cameras incorporates an ARM 1136J-S RISC processor core plus separate image and video processors
- EMA Design Automation announces FootprintGen—an app for Cadence Allegro and OrCAD PCB design tools that cuts the time needed to design PCB footprint models for new components
- 3D Thursday: 28nm design and 2.5D packaging saves Xilinx a ton of power. You can too even if you're not designing FPGAs!
- Clock Concurrent Optimization: The Primer to the Primer—OR—Want to overcome some major functional hurdles to Silicon Realization and save a lot of power on your SoC at the same time?
- 39 low-cost boards for embedded Linux application development starting with Raspberry Pi. Want the list?
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Tag Archives: CMOS
3D Thursday: My breakfast with IBM’s Gary Patton leads to a discussion of 20nm and 14nm IC design
Yesterday I moderated a panel on 2(x)nm success at DAC and one of the panelists was Dr. Gary Patton, VP of IBM’s Semiconductor Research and Development Center in East Fishkill, NY. I’ve heard Dr. Patton speak before and he knows … Continue reading
Posted in 14nm, 20nm, 28nm, Double Patterning, EDA360, EUV, Silicon Realization, SoC, SoC Realization
Tagged Bipolar, CMOS, Extreme ultraviolet, FinFET, Gary Patton, IBM, Multiple patterning, TriGate
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ICCAD Keynote: Design of Secure Systems – Where are the EDA Tools?
Georg Sigl has spent ten years looking at system security and developing secure ICs for a variety of applications. Starting in the year 2000, he was responsible for developing new secure microcontroller platforms in the Chip Card and Security division … Continue reading
Posted in Silicon Realization, SoC, SoC Realization
Tagged CMOS, Security, Side channel attack, Smart card
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