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Recent Posts
- A head-to-head comparison of the ARM Cortex-M4 and –M0 processor cores by Jack Ganssle
- Friday Video: SoC in tiny 500mg backpack transforms cockroach into radio-controlled exploration vehicle
- Friday Video: A different kind of fab with some very, very cool machines
- Friday Video: Get the latest skinny on the IPC-2581 open interchange standard for PCB design
- Smartphones: Where PCIe has not gone before—but will. Sooner rather than later.
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Top Posts
- A head-to-head comparison of the ARM Cortex-M4 and –M0 processor cores by Jack Ganssle
- ARM Cortex-A15—does this processor IP core need a new category…Superstar IP?
- The DDR4 SDRAM spec and SoC design. What do we know now?
- Gartner’s Sam Wang tosses down the 28nm Silicon Realization gauntlet to IC design houses
- Is 28nm really here? Now? When?
- New apps for pcb designers in the OrCad Capture Marketplace speed common design tasks
- 3-processor SoC for digital still cameras incorporates an ARM 1136J-S RISC processor core plus separate image and video processors
- Generation-jumping 2.5D Xilinx Virtex-7 2000T FPGA delivers 1,954,560 logic cells using 6.8 BILLION transistors (PREVIEW!)
- 39 low-cost boards for embedded Linux application development starting with Raspberry Pi. Want the list?
- Between ASIC and microcontroller: It’s all about System Realization
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Tag Archives: Common Technology Platform Forum
Hear IBM’s Dr. Gary Patton on the future of silicon scaling…and beyond. (Audio from The Common Technology Platform Forum keynote)
Earlier this year, Dr. Gary Patton, Vice President of IBM’s Semiconductor Research and Development Center, spoke about the future of semiconductor scaling and beyond. It was a terrific keynote speech at the Common Platform Technology Forum and was similar to … Continue reading
Posted in 10nm, 14nm, 20nm, 3D, EDA360, IBM, Silicon Realization
Tagged Common Technology Platform Forum, Gary Patton, IBM
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