Tag Archives: CoWoS

3D Thursday: Want to see a closeup of the TSMC 3D IC test vehicle?

Posted on June 6, 2012 by sleibson2

Richard Goering just published a detailed blog post about the TSMC 2.5D/3D IC test vehicle, which TSMC is calling CoWoS (Chip on Wafer on Substrate) in his Industry Insights blog. This approach to 3D IC assembly bonds active silicon die … Continue reading →

Posted in 2.5D, 3D, TSMC | Tagged , , | Leave a comment

3D Thursday: Practical Approaches to 3-D IC—TSV/Silicon Interposer and Wide IO Implementation From People Who Have Been There, Done That

Posted on May 2, 2012 by sleibson2

If you’re like me, you’ve heard more than enough theory about 3D IC assembly and you’re ready to get on with the main event and design something. Want to hear about 3D IC technology that works? Now? Then you will … Continue reading →

Posted in 2.5D, 3D, Packaging, Silicon Realization, TSMC | Tagged , , , , , | Leave a comment