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- A head-to-head comparison of the ARM Cortex-M4 and –M0 processor cores by Jack Ganssle
- Friday Video: SoC in tiny 500mg backpack transforms cockroach into radio-controlled exploration vehicle
- Friday Video: A different kind of fab with some very, very cool machines
- Friday Video: Get the latest skinny on the IPC-2581 open interchange standard for PCB design
- Smartphones: Where PCIe has not gone before—but will. Sooner rather than later.
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Top Posts
- A head-to-head comparison of the ARM Cortex-M4 and –M0 processor cores by Jack Ganssle
- EDA360 and the brand new Hewlett-Packard 15C Limited Edition RPN pocket scientific calculator
- Ingenious architectural features allow ST to extract maximum performance from new microcontroller family based on ARM Cortex-M4. Cost: less than 6 bucks in 1000s
- 3-processor SoC for digital still cameras incorporates an ARM 1136J-S RISC processor core plus separate image and video processors
- Realizing the ARM Cortex-A15: What does the road to 2.5GHz look like?
- The DDR4 SDRAM spec and SoC design. What do we know now?
- Where is the mainstream IC process technology today? 28nm? 40nm? 65nm?
- Friday Video (late): Fully operational “Lost in Space” B9 Robot, $24500
- Cadence announces synthesizable 40G and 100G Ethernet Controller, PCS, and BEAN (Backplane Ethernet Auto-Negotiation) IP
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Tag Archives: Design Compiler
Gary Smith proposes a 3-layer taxonomy for platform-based SoC design—Live from DAC 2012
EDA’s chief analyst Gary Smith is high on IP subsystems—big ones. Only Gary calls them platforms. Why is Smith so enthusiastic? Because, as he says, he was wrong last year in his estimates of how much it costs to develop … Continue reading
Posted in DAC, IP, SoC, SoC Realization, System Realization, Texas instruments
Tagged ARM, Armada, Design Compiler, Marvell, Nvidia, OMAP, Qualcomm, Snapdragon, Tegra
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