Tag Archives: Design rule checking

20nm design: What have we learned so far?

Even if you are not currently considering 20nm design, you owe it to yourself to download and read a new 9-page White Paper titled “A Call to Action: How 20nm Will Change IC Design” to learn about some tectonic shifts … Continue reading

Posted in 20nm, 28nm, AMS, Analog, ARM, Design Abstraction, EDA360, Silicon Realization, Verification | Tagged , , , , , , , | 1 Comment

Who else wants to see a 60x speedup in DFM signoff on a 28nm design?

Rambus has announced that it achieved a 60x speedup in DRC for an IP design targeting a 28nm process technology using GLOBALFOUNDRIES’ DRC+ methodology. This approach to DRC is interesting because it’s the industry’s first approach to DRC that teams … Continue reading

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