Tag Archives: DFT

3D Thursday: Mark LaPedus writes overview of the 3D IC landscape

Briefly noted: Over at the Semiconductor Manufacturing & Design Community, Senior Editor Mark LaPedus has just published an article that’s a good review of the various challenges to 3D IC adoption including: Known good die Testability Design for test Standards … Continue reading

Posted in 2.5D, 3D, EDA360, Silicon Realization, SoC, SoC Realization | Tagged , , , | Leave a comment