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- A head-to-head comparison of the ARM Cortex-M4 and –M0 processor cores by Jack Ganssle
- Friday Video: SoC in tiny 500mg backpack transforms cockroach into radio-controlled exploration vehicle
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- Friday Video: Get the latest skinny on the IPC-2581 open interchange standard for PCB design
- Smartphones: Where PCIe has not gone before—but will. Sooner rather than later.
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Top Posts
- A head-to-head comparison of the ARM Cortex-M4 and –M0 processor cores by Jack Ganssle
- 3-processor SoC for digital still cameras incorporates an ARM 1136J-S RISC processor core plus separate image and video processors
- 3D Thursday: Micron’s 3D Hybrid Memory Cube delivers more DRAM bandwidth at lower power and in a smaller form factor using TSVs
- Collaboration is key to making DFM work at 28nm and below
- 3D Thursday: A look at some genuine 3D NAND cells, courtesy of Micron
- Friday Video: How many hardware/software integration lessons can you absorb in 34 minutes?
- The DDR4 SDRAM spec and SoC design. What do we know now?
- Clock Concurrent Optimization: The Primer to the Primer—OR—Want to overcome some major functional hurdles to Silicon Realization and save a lot of power on your SoC at the same time?
- Intel’s Knut Grimsrud explains how to get another 20x improvement in SSD performance
- Where is the mainstream IC process technology today? 28nm? 40nm? 65nm?
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Tag Archives: Doubletree
By the numbers: 20nm (and 40nm, 32nm, 28nm, and 14nm) design to be discussed in technical detail at next week’s CDNLive! conference in Silicon Valley
There’s still time to register for CDNLive!, which is being held on March 13 and 14 at the Doubletree Hotel in San Jose, California so let me give you a few numbers to whet your appetite: 40nm, 32nm, 28nm, 20nm, … Continue reading
Posted in 14nm, 20nm, 28nm, 32nm, 40nm, CDNLive!, EDA360, Silicon Realization, SoC, SoC Realization, System Realization
Tagged 14nm, 20nm, 28nm, 32nm, 40nm, CDNLive!, Double Patterning, Doubletree, GlobalFoundries, IBM, Samsung
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