Tag Archives: Electronic design automation

Workshop on Analog and Mixed-Signal Design Automation: November 8 in Silicon Valley

Posted on August 23, 2012 by

A 1-day workshop on Analog and Mixed-Signal Design Automation will be held on November 8 in conjunction with ICCAD in Silicon Valley. It’s no secret that advanced-node process scaling makes all IC design more complex and more challenging—even more so … Continue reading →

Posted in EDA360, Mixed Signal, Silicon Realization | Tagged , , , , , , , | Leave a comment

20nm design: What have we learned so far?

Posted on July 10, 2012 by

Even if you are not currently considering 20nm design, you owe it to yourself to download and read a new 9-page White Paper titled “A Call to Action: How 20nm Will Change IC Design” to learn about some tectonic shifts … Continue reading →

Posted in 20nm, 28nm, AMS, Analog, ARM, Design Abstraction, EDA360, Silicon Realization, Verification | Tagged , , , , , , , | 1 Comment

Some chip-design reality from Mentor’s Wally Rhines at last week’s annual DAC ESL panel

Posted on June 11, 2012 by

Last week at DAC, Mentor’s Chairman and CEO Wally Rhines chaired a panel on ESL but in his introduction, Wally spoke more about chip-design costs and associated software development. “The rapidly escalating cost of chip design has more to do … Continue reading →

Posted in EDA360, ESL, SoC, SoC Realization, System Realization | Tagged , , , | 1 Comment

Do you need to improve verification performance for advanced-node SoCs? Learn how on May 14 in Munich.

Posted on April 25, 2012 by

The state space of a chip grows exponentially every 24 months. That’s the verification corollary to Moore’s Law. Verification engineers tackle the problem with faster simulation but that’s no longer enough. The complete verification cycle includes compilation/elaboration; RTL/gate/SV/e/SystemC mixed-mode simulation; … Continue reading →

Posted in EDA360, Silicon Realization, SoC Realization, System Realization, Verification | Tagged , , , | Leave a comment

Less than two weeks left for early-bird EDPS registration. Don’t miss 3D Friday, the other EDA speakers, or your chance to network for that matter

Posted on March 6, 2012 by

EDPS (The Electronic Design Process Symposium) provides a dynamic venue for the exchange of ideas among the top thinkers, movers, and shakers in EDA, who focus on how chips and systems are designed in the electronics industry. Attendees of this … Continue reading →

Posted in 3D, EDA360 | Tagged , , , | Leave a comment

EDA Consultant? Here’s your chance to strut your stuff in front of a prime audience

Posted on November 4, 2011 by

If you are an EDA consultant looking for clients, then marketing takes a chunk of your time. How about some prime face time in front of hundreds of prospects? If you are an expert in working with Cadence EDA tools … Continue reading →

Posted in EDA360 | Tagged , , | Leave a comment