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Recent Posts
- A head-to-head comparison of the ARM Cortex-M4 and –M0 processor cores by Jack Ganssle
- Friday Video: SoC in tiny 500mg backpack transforms cockroach into radio-controlled exploration vehicle
- Friday Video: A different kind of fab with some very, very cool machines
- Friday Video: Get the latest skinny on the IPC-2581 open interchange standard for PCB design
- Smartphones: Where PCIe has not gone before—but will. Sooner rather than later.
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Top Posts
- A head-to-head comparison of the ARM Cortex-M4 and –M0 processor cores by Jack Ganssle
- 3D Thursday: More on the Xilinx Virtex 7 with 2.5D tiling. Wave of the future or stopgap measure?
- 20nm design: What have we learned so far?
- Ingenious architectural features allow ST to extract maximum performance from new microcontroller family based on ARM Cortex-M4. Cost: less than 6 bucks in 1000s
- The WORD on ARM’s big.LITTLE Cortex-A15/A7 design philosophy from Jack Ganssle, a leading expert and consultant on embedded design and firmware development
- Smartphones: Where PCIe has not gone before—but will. Sooner rather than later.
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Tag Archives: Electronic design automation
Workshop on Analog and Mixed-Signal Design Automation: November 8 in Silicon Valley
A 1-day workshop on Analog and Mixed-Signal Design Automation will be held on November 8 in conjunction with ICCAD in Silicon Valley. It’s no secret that advanced-node process scaling makes all IC design more complex and more challenging—even more so … Continue reading
20nm design: What have we learned so far?
Even if you are not currently considering 20nm design, you owe it to yourself to download and read a new 9-page White Paper titled “A Call to Action: How 20nm Will Change IC Design” to learn about some tectonic shifts … Continue reading
Some chip-design reality from Mentor’s Wally Rhines at last week’s annual DAC ESL panel
Last week at DAC, Mentor’s Chairman and CEO Wally Rhines chaired a panel on ESL but in his introduction, Wally spoke more about chip-design costs and associated software development. “The rapidly escalating cost of chip design has more to do … Continue reading
Do you need to improve verification performance for advanced-node SoCs? Learn how on May 14 in Munich.
The state space of a chip grows exponentially every 24 months. That’s the verification corollary to Moore’s Law. Verification engineers tackle the problem with faster simulation but that’s no longer enough. The complete verification cycle includes compilation/elaboration; RTL/gate/SV/e/SystemC mixed-mode simulation; … Continue reading
Less than two weeks left for early-bird EDPS registration. Don’t miss 3D Friday, the other EDA speakers, or your chance to network for that matter
EDPS (The Electronic Design Process Symposium) provides a dynamic venue for the exchange of ideas among the top thinkers, movers, and shakers in EDA, who focus on how chips and systems are designed in the electronics industry. Attendees of this … Continue reading
EDA Consultant? Here’s your chance to strut your stuff in front of a prime audience
If you are an EDA consultant looking for clients, then marketing takes a chunk of your time. How about some prime face time in front of hundreds of prospects? If you are an expert in working with Cadence EDA tools … Continue reading
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