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- A head-to-head comparison of the ARM Cortex-M4 and –M0 processor cores by Jack Ganssle
- Friday Video: SoC in tiny 500mg backpack transforms cockroach into radio-controlled exploration vehicle
- Friday Video: A different kind of fab with some very, very cool machines
- Friday Video: Get the latest skinny on the IPC-2581 open interchange standard for PCB design
- Smartphones: Where PCIe has not gone before—but will. Sooner rather than later.
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Top Posts
- A head-to-head comparison of the ARM Cortex-M4 and –M0 processor cores by Jack Ganssle
- Download a free PDF of the Mixed-signal Methodology Guide, Chapter 1: Design Trends and Challenges
- ARM Cortex-A15—does this processor IP core need a new category…Superstar IP?
- Is the Common Platform Alliance a credible competitor to TSMC?
- ARM drops Cortex-A7 core on unsuspecting market, devastates low-power SoC and application-processor landscapes. What’s it all mean?
- If Aladdin’s Genie lived in a Computer-on-Module, it might look like the Gumstix Overo
- Intel’s Knut Grimsrud explains how to get another 20x improvement in SSD performance
- What would you do with a 23,000-simultaneous-thread school of piranha?...asks NVIDIA
- Ingenious architectural features allow ST to extract maximum performance from new microcontroller family based on ARM Cortex-M4. Cost: less than 6 bucks in 1000s
- Experimental , ultra-low-power 1.2V, 65nm SoC from ST and MIT operates at 82.5MHz (!) maximum, 540KHz at 0.54V
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Tag Archives: Ethernet
How Skyera developed the 44Tbyte, enterprise-class Skyhawk SSD from the ground up. A System Realization story.
I rarely get to tell an in-depth System Realization story like this one. The development of the 44Tbyte, enterprise-class Skyhawk SSD starts with a clear picture of the objective—build an enterprise-class, solid-state storage server using commercial MLC (multi-level cell) NAND … Continue reading
Posted in EDA360, System Realization
Tagged Ethernet, Flash, Flash memory, Multi-level cell, NAND Flash, RAID, Skyera, Solid-state drive, SSD
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Networks on Chip: Redux, Redux, Redux
There must be some way out of here Said the joker to the thief There’s too much confusion I can’t get no relief – “All Along the Watchtower,” Bob Dylan During the late 1980s and early 1990s, we had around … Continue reading
Posted in EDA360, Silicon Realization, SoC, SoC Realization
Tagged Babel, Bob Dylan, Ethernet, Massachusetts Institute of Technology, MIT, Network On Chip, NoC, SoC
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3D Thursday: How about a closeup of the Avago MiniPOD optical interconnect on the Altera Optical FPGA?
I just posted a blog entry about the Altera Optical FPGA that pumped 100Gigabit/sec Ethernet (GbE) traffic through a 3D-package-on-package-mounted, 12-channel optical interconnect device from Avago. (See “3D Thursday: Altera adds Avago MicroPOD optical interconnects to FPGA package to handle … Continue reading
Posted in 3D, EDA360
Tagged 100 Gigabit Ethernet, Altera, Avago, Ethernet, FPGA, Gigabit Ethernet, Optical interconnect
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3D Thursday: 40G and 100G optical Ethernet—Killer 3D app? Perhaps. Compelling? Definitely.
I’ve written several times about Wide I/O DRAM and how its speed and power advantages make it a slam dunk and killer app for 3D IC assembly. I saw another such 3D IC killer app this week at the Ethernet … Continue reading
Posted in 2.5D, 3D, EDA360, Silicon Realization, SoC, SoC Realization, System Realization
Tagged 100 Gigabit Ethernet, 100G, 40G, AOC, Ethernet, Luxtera, MSA, PHY, Xilinx
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Cadence announces synthesizable 40G and 100G Ethernet Controller, PCS, and BEAN (Backplane Ethernet Auto-Negotiation) IP
In conjunction with this week’s Ethernet Technology Summit being held in San Jose, Cadence has announced commercial availability of MAC (Media Access Control), PCS (Physical Coding Sublayer) and BEAN (Backplane Ethernet Auto-Negotiation) IP blocks. The 40/100G MAC controller is fully … Continue reading
Posted in EDA360, Silicon Realization, SoC, SoC Realization
Tagged 100 Gigabit Ethernet, 100G, 40G, Ethernet, Gigabit Ethernet, Media Access Control, MII, PCS, PHY, SerDes, Verilog
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