Tag Archives: ETSOI

GLOBALFOUNDRIES talks FinFETs, EUV, 14nm, ETSOI. Any other bleeding-edge chipmaking terms you wanted to hear?

Near the end of his Global Technology Conference presentation last week, Senior VP of Technology and R&D Gregg Bartlett jumped to the future—namely 2014 to 2015. By then, GLOBALFOUNDRIES plans to be implementing the second production phase for its 20nm … Continue reading

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Are FinFETs inevitable at 20nm? “Yes, no, maybe” says Professor Chenming Hu (Part 2)

Yesterday’s blog entry discussed FinFETs as a way to build advanced-process transistors with reduced leakage and improved performance. (See “Are FinFETs inevitable at 20nm? “Yes, no, maybe” says Professor Chenming Hu (Part 1)“.) There’s another way to eliminate the unwanted … Continue reading

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Are FinFETs inevitable at 20nm? “Yes, no, maybe” says Professor Chenming Hu

Intel announced in early May that it would be using “Tri-Gate” FETs to build microprocessors at the 22nm node. (See the previous EDA360 Insider post “3D Thursday: Intel and FinFETs (Tri-Gate transistors)—a different kind of 3D”). Intel’s Tri-Gate transistor structures … Continue reading

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