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Top Posts
- A head-to-head comparison of the ARM Cortex-M4 and –M0 processor cores by Jack Ganssle
- EDA360 and the brand new Hewlett-Packard 15C Limited Edition RPN pocket scientific calculator
- EMA Design Automation announces FootprintGen—an app for Cadence Allegro and OrCAD PCB design tools that cuts the time needed to design PCB footprint models for new components
- ARM big.LITTLE multicore IP architecture wins a Microprocessor Report Analysts’ Choice Award
- Two more low-cost dev boards based on the ARM Cortex-M4 with 1Mbyte of Flash, 192Kbytes of RAM: $15.57 and up
- Download a free PDF of the Mixed-signal Methodology Guide, Chapter 1: Design Trends and Challenges
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Tag Archives: EUV
What are the challenges of EUV lithography and the issues surrounding double patterning? CDNLive! presentation provides details.
Richard Goering has just published an excellent blog post on double patterning for 20nm and 14nm process geometries in his blog Industry Insights. The post is based on a paper presented by IBM Distinguished Engineer Lars Liebman at the recent … Continue reading
Posted in 14nm, 20nm, Double Patterning, EDA360, EUV, Silicon Realization
Tagged 20nm 14nm, Double Patterning, EUV, Extreme ultraviolet lithography, IBM, Lithography, Microprocessor Report
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GLOBALFOUNDRIES talks FinFETs, EUV, 14nm, ETSOI. Any other bleeding-edge chipmaking terms you wanted to hear?
Near the end of his Global Technology Conference presentation last week, Senior VP of Technology and R&D Gregg Bartlett jumped to the future—namely 2014 to 2015. By then, GLOBALFOUNDRIES plans to be implementing the second production phase for its 20nm … Continue reading
Posted in EDA360, Globalfoundries, Silicon Realization
Tagged 14nm, 20nm, ETSOI, EUV, FinFET
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