Tag Archives: FPGA

3D Thursday: 3D-IC Design Tools and Services Tour Guide is just in time for DAC. You can download a copy now.

The GSA has just issued a 3D-IC tools and services guide in time for DAC. This 62-page guide provides eight pages of background info on the state of 3D assembly technology based on public information like that provided by Xilinx … Continue reading

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Friday video (late bonus): Altera demos some features from 28nm Stratix V FPGA

On Friday, Altera posted a video that shows the company characterizing some of the features of the upcoming Stratix V FPGA, being built with a 28nm process technology. The largest member of the Stratix V FPGA family will incorporate nearly … Continue reading

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3D Thursday: More on the Xilinx Virtex 7 with 2.5D tiling. Wave of the future or stopgap measure?

Last November, I wrote a blog entry about Xilinx’ plan to use 2.5D assembly techniques to create large Virtex 7 FPGAs using tiled 28nm silicon with interposers. (See “Need really big FPGAs? Xilinx will be taking the “3D” route for … Continue reading

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Friday video (2fer): 28nm FPGA videos from Xilinx and Altera

Recently, Xilinx announced shipping early samples of its 28nm Kintex-7 FPGAs. Now 28nm is the current bleeding-edge process node for logic processes and it’s no small feat to start shipping parts—even early engineering samples—at this node. Here’s a video of … Continue reading

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Altera purchases optical network IP vendor Avalon Microelectronics

In a move characterized as “not a material financial matter,” FPGA vendor Altera has announced the purchase of Avalon Microelectronics, a Canadian vendor of FPGA-centric IP used to design optical networking equipment. Networking has long been a mainstay application for … Continue reading

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Need really big FPGAs? Xilinx will be taking the “3D” route for initial Virtex 7 parts

Ivo Bolsens, the Xilinx CTO and Senior VP, presented a keynote at the 8th International SoC Conference a couple of weeks ago and one of the aspects of FPGA development that he discussed was Xilinx’ plan for creating large-capacity Virtex … Continue reading

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Will verification challenges overwhelm FPGA design?

EETimes just published a blog titled “FPGAs advance, but verification challenges increase,” written by GateRocket’s president and CEO Dave Orecchio. The article makes the point that FPGAs are rapidly losing their “easy-to-use” market positioning because, to put it quite simply, … Continue reading

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