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- Friday Video: SoC in tiny 500mg backpack transforms cockroach into radio-controlled exploration vehicle
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Top Posts
- Ingenious architectural features allow ST to extract maximum performance from new microcontroller family based on ARM Cortex-M4. Cost: less than 6 bucks in 1000s
- A head-to-head comparison of the ARM Cortex-M4 and –M0 processor cores by Jack Ganssle
- Realizing the ARM Cortex-A15: What does the road to 2.5GHz look like?
- Free Webinar teaches you how to mix C, C++, SystemC, and SystemVerilog verification models within UVM—October 20
- Download a free PDF of the Mixed-signal Methodology Guide, Chapter 1: Design Trends and Challenges
- Friday Video: Circuit simulation app for Android. SPICE for $10, runs in your hand? Well, almost.
- 3D Thursday: Micron to present Hybrid Memory Cube status at EDPS in Monterey, April 6—there’s a lot of news
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Tag Archives: Functional verification
Need a better way to visualize and track verification metrics? Learn how this Wednesday. Free.
You have only hours to sign up for a free Webinar on using the Cadence Incisive Metric Center taking place this coming Wednesday at noon (US Eastern Time). “What’s that?” you might ask. The Incisive Metrics Center simplifies the way … Continue reading
Do you need to improve verification performance for advanced-node SoCs? Learn how on May 14 in Munich.
The state space of a chip grows exponentially every 24 months. That’s the verification corollary to Moore’s Law. Verification engineers tackle the problem with faster simulation but that’s no longer enough. The complete verification cycle includes compilation/elaboration; RTL/gate/SV/e/SystemC mixed-mode simulation; … Continue reading
Want a shortcut to automating assertion generation for simulation, formal verification, and emulation flows?
Assertion-based verification (ABV) helps ASIC and SoC design and verification teams using simulation, formal analysis, and emulation methodologies accelerate verification signoff by enhancing the RTL and test specifications to include assertions and functional coverage properties, which are logic statements that … Continue reading
Posted in EDA360, System Realization, Verification
Tagged assertion, Functional verification
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