Search EDA360 Insider
Hey!!! Subscribe now to the EDA360 Insider!
-
Recent Posts
- A head-to-head comparison of the ARM Cortex-M4 and –M0 processor cores by Jack Ganssle
- Friday Video: SoC in tiny 500mg backpack transforms cockroach into radio-controlled exploration vehicle
- Friday Video: A different kind of fab with some very, very cool machines
- Friday Video: Get the latest skinny on the IPC-2581 open interchange standard for PCB design
- Smartphones: Where PCIe has not gone before—but will. Sooner rather than later.
EDA360 Tag Cloud
- 2.5D
- 3D
- 3D IC
- 20nm
- 28nm
- 32nm
- 40nm
- Agilent
- Altera
- AMD
- Analog
- Android
- Apple
- ARM
- ARM architecture
- ARM Cortex-A15
- ASIC
- Broadcom
- Cadence
- Canon
- Cortex
- Cortex-A15
- Cortex-M0
- DAC
- Dave Jones
- DDR3
- DDR4
- Double Patterning
- EDA
- EDPS
- Field-programmable gate array
- FinFET
- Flash
- Flash memory
- FPGA
- Freescale
- Freescale Semiconductor
- GlobalFoundries
- IBM
- Intel
- IP
- iPad
- iPhone
- JEDEC
- Jim Hogan
- Kinect
- Linux
- Low Power
- Lytro
- microcontroller
- Micron
- Microsoft
- Mixed Signal
- Multi-core processor
- Nvidia
- OrCAD
- pcb
- Printed circuit board
- Qualcomm
- Robot
- Samsung
- SDRAM
- Snapdragon
- SoC
- STMicroelectronics
- SystemC
- Texas Instruments
- TI
- TSMC
- USB
- verification
- video
- Wide I/O
- Xilinx
Top Posts
- A head-to-head comparison of the ARM Cortex-M4 and –M0 processor cores by Jack Ganssle
- Want to know more about the Micron Hybrid Memory Cube (HMC)? How about its terabit/sec data rate?
- Download a free PDF of the Mixed-signal Methodology Guide, Chapter 1: Design Trends and Challenges
- How DAC Got Started: Richard Goering interviews Kaufman Award Winner Pat Pistilli
- EDA360 and the brand new Hewlett-Packard 15C Limited Edition RPN pocket scientific calculator
- Ingenious architectural features allow ST to extract maximum performance from new microcontroller family based on ARM Cortex-M4. Cost: less than 6 bucks in 1000s
- Apps define storage task, create application-specific SSD
Download the EDA360 Vision Paper here:
Tag Archives: Functional verification
Need a better way to visualize and track verification metrics? Learn how this Wednesday. Free.
You have only hours to sign up for a free Webinar on using the Cadence Incisive Metric Center taking place this coming Wednesday at noon (US Eastern Time). “What’s that?” you might ask. The Incisive Metrics Center simplifies the way … Continue reading
Do you need to improve verification performance for advanced-node SoCs? Learn how on May 14 in Munich.
The state space of a chip grows exponentially every 24 months. That’s the verification corollary to Moore’s Law. Verification engineers tackle the problem with faster simulation but that’s no longer enough. The complete verification cycle includes compilation/elaboration; RTL/gate/SV/e/SystemC mixed-mode simulation; … Continue reading
Want a shortcut to automating assertion generation for simulation, formal verification, and emulation flows?
Assertion-based verification (ABV) helps ASIC and SoC design and verification teams using simulation, formal analysis, and emulation methodologies accelerate verification signoff by enhancing the RTL and test specifications to include assertions and functional coverage properties, which are logic statements that … Continue reading
Posted in EDA360, System Realization, Verification
Tagged assertion, Functional verification
Leave a comment
EDA360 Insider 