Tag Archives: Functional verification

Need a better way to visualize and track verification metrics? Learn how this Wednesday. Free.

Posted on June 25, 2012 by

You have only hours to sign up for a free Webinar on using the Cadence Incisive Metric Center taking place this coming Wednesday at noon (US Eastern Time). “What’s that?” you might ask. The Incisive Metrics Center simplifies the way … Continue reading →

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Do you need to improve verification performance for advanced-node SoCs? Learn how on May 14 in Munich.

Posted on April 25, 2012 by

The state space of a chip grows exponentially every 24 months. That’s the verification corollary to Moore’s Law. Verification engineers tackle the problem with faster simulation but that’s no longer enough. The complete verification cycle includes compilation/elaboration; RTL/gate/SV/e/SystemC mixed-mode simulation; … Continue reading →

Posted in EDA360, Silicon Realization, SoC Realization, System Realization, Verification | Tagged , , , | Leave a comment

Want a shortcut to automating assertion generation for simulation, formal verification, and emulation flows?

Posted on October 6, 2011 by

Assertion-based verification (ABV) helps ASIC and SoC design and verification teams using simulation, formal analysis, and emulation methodologies accelerate verification signoff by enhancing the RTL and test specifications to include assertions and functional coverage properties, which are logic statements that … Continue reading →

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