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- A head-to-head comparison of the ARM Cortex-M4 and –M0 processor cores by Jack Ganssle
- Friday Video: SoC in tiny 500mg backpack transforms cockroach into radio-controlled exploration vehicle
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- Friday Video: Get the latest skinny on the IPC-2581 open interchange standard for PCB design
- Smartphones: Where PCIe has not gone before—but will. Sooner rather than later.
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Top Posts
- A head-to-head comparison of the ARM Cortex-M4 and –M0 processor cores by Jack Ganssle
- Where is the mainstream IC process technology today? 28nm? 40nm? 65nm?
- EDA360 and the brand new Hewlett-Packard 15C Limited Edition RPN pocket scientific calculator
- Ingenious architectural features allow ST to extract maximum performance from new microcontroller family based on ARM Cortex-M4. Cost: less than 6 bucks in 1000s
- 3-processor SoC for digital still cameras incorporates an ARM 1136J-S RISC processor core plus separate image and video processors
- EMA Design Automation announces FootprintGen—an app for Cadence Allegro and OrCAD PCB design tools that cuts the time needed to design PCB footprint models for new components
- 3D Thursday: 28nm design and 2.5D packaging saves Xilinx a ton of power. You can too even if you're not designing FPGAs!
- Clock Concurrent Optimization: The Primer to the Primer—OR—Want to overcome some major functional hurdles to Silicon Realization and save a lot of power on your SoC at the same time?
- 39 low-cost boards for embedded Linux application development starting with Raspberry Pi. Want the list?
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Tag Archives: Functional verification
Need a better way to visualize and track verification metrics? Learn how this Wednesday. Free.
You have only hours to sign up for a free Webinar on using the Cadence Incisive Metric Center taking place this coming Wednesday at noon (US Eastern Time). “What’s that?” you might ask. The Incisive Metrics Center simplifies the way … Continue reading
Do you need to improve verification performance for advanced-node SoCs? Learn how on May 14 in Munich.
The state space of a chip grows exponentially every 24 months. That’s the verification corollary to Moore’s Law. Verification engineers tackle the problem with faster simulation but that’s no longer enough. The complete verification cycle includes compilation/elaboration; RTL/gate/SV/e/SystemC mixed-mode simulation; … Continue reading
Want a shortcut to automating assertion generation for simulation, formal verification, and emulation flows?
Assertion-based verification (ABV) helps ASIC and SoC design and verification teams using simulation, formal analysis, and emulation methodologies accelerate verification signoff by enhancing the RTL and test specifications to include assertions and functional coverage properties, which are logic statements that … Continue reading
Posted in EDA360, System Realization, Verification
Tagged assertion, Functional verification
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