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Tag Archives: Gary Patton
Hear IBM’s Dr. Gary Patton on the future of silicon scaling…and beyond. (Audio from The Common Technology Platform Forum keynote)
Earlier this year, Dr. Gary Patton, Vice President of IBM’s Semiconductor Research and Development Center, spoke about the future of semiconductor scaling and beyond. It was a terrific keynote speech at the Common Platform Technology Forum and was similar to … Continue reading
Posted in 10nm, 14nm, 20nm, 3D, EDA360, IBM, Silicon Realization
Tagged Common Technology Platform Forum, Gary Patton, IBM
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3D Thursday: My breakfast with IBM’s Gary Patton leads to a discussion of 20nm and 14nm IC design
Yesterday I moderated a panel on 2(x)nm success at DAC and one of the panelists was Dr. Gary Patton, VP of IBM’s Semiconductor Research and Development Center in East Fishkill, NY. I’ve heard Dr. Patton speak before and he knows … Continue reading
Posted in 14nm, 20nm, 28nm, Double Patterning, EDA360, EUV, Silicon Realization, SoC, SoC Realization
Tagged Bipolar, CMOS, Extreme ultraviolet, FinFET, Gary Patton, IBM, Multiple patterning, TriGate
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