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Recent Posts
- A head-to-head comparison of the ARM Cortex-M4 and –M0 processor cores by Jack Ganssle
- Friday Video: SoC in tiny 500mg backpack transforms cockroach into radio-controlled exploration vehicle
- Friday Video: A different kind of fab with some very, very cool machines
- Friday Video: Get the latest skinny on the IPC-2581 open interchange standard for PCB design
- Smartphones: Where PCIe has not gone before—but will. Sooner rather than later.
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- Ingenious architectural features allow ST to extract maximum performance from new microcontroller family based on ARM Cortex-M4. Cost: less than 6 bucks in 1000s
- A head-to-head comparison of the ARM Cortex-M4 and –M0 processor cores by Jack Ganssle
- ARM Cortex-A15—does this processor IP core need a new category…Superstar IP?
- 39 low-cost boards for embedded Linux application development starting with Raspberry Pi. Want the list?
- 3D Thursday: Micron’s 3D Hybrid Memory Cube delivers more DRAM bandwidth at lower power and in a smaller form factor using TSVs
- Samsung Exynos 5 Dual mobile processor features two 1.7GHz ARM Cortex-A15 processors, a WQXGA display controller, and two LPDDR3 controllers to feed ‘em
- How about a quick and easy guide to ARM Cortex processor cores? Got one for you from ARM TechCon 2011
- Want to know more about the Micron Hybrid Memory Cube (HMC)? How about its terabit/sec data rate?
- Samsung extends Android Galaxy to a credible point-and-shoot camera
- Friday Video: The Easter Egg in the Agilent InfiniiVision 3000 X-Series DSO
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Tag Archives: Gigabit Ethernet
3D Thursday: How about a closeup of the Avago MiniPOD optical interconnect on the Altera Optical FPGA?
I just posted a blog entry about the Altera Optical FPGA that pumped 100Gigabit/sec Ethernet (GbE) traffic through a 3D-package-on-package-mounted, 12-channel optical interconnect device from Avago. (See “3D Thursday: Altera adds Avago MicroPOD optical interconnects to FPGA package to handle … Continue reading
Posted in 3D, EDA360
Tagged 100 Gigabit Ethernet, Altera, Avago, Ethernet, FPGA, Gigabit Ethernet, Optical interconnect
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Cadence announces synthesizable 40G and 100G Ethernet Controller, PCS, and BEAN (Backplane Ethernet Auto-Negotiation) IP
In conjunction with this week’s Ethernet Technology Summit being held in San Jose, Cadence has announced commercial availability of MAC (Media Access Control), PCS (Physical Coding Sublayer) and BEAN (Backplane Ethernet Auto-Negotiation) IP blocks. The 40/100G MAC controller is fully … Continue reading
Posted in EDA360, Silicon Realization, SoC, SoC Realization
Tagged 100 Gigabit Ethernet, 100G, 40G, Ethernet, Gigabit Ethernet, Media Access Control, MII, PCS, PHY, SerDes, Verilog
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