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Recent Posts
- A head-to-head comparison of the ARM Cortex-M4 and –M0 processor cores by Jack Ganssle
- Friday Video: SoC in tiny 500mg backpack transforms cockroach into radio-controlled exploration vehicle
- Friday Video: A different kind of fab with some very, very cool machines
- Friday Video: Get the latest skinny on the IPC-2581 open interchange standard for PCB design
- Smartphones: Where PCIe has not gone before—but will. Sooner rather than later.
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Top Posts
- A head-to-head comparison of the ARM Cortex-M4 and –M0 processor cores by Jack Ganssle
- 10 ways to get your EDA tools to run faster, smoother, and longer
- Ingenious architectural features allow ST to extract maximum performance from new microcontroller family based on ARM Cortex-M4. Cost: less than 6 bucks in 1000s
- How many people does it take to design an SoC? – Redux. Building brains with processors.
- Are FinFETs inevitable at 20nm? “Yes, no, maybe” says Professor Chenming Hu (Part 2)
- Friday Video (Musical Bonus): What does it take to play the Dr. Who theme song with a pair of Tesla coils, a Faraday cage, and two unlucky audience members?
- Qualcomm reveals more Snapdragon 4 SoC details in a White Paper. Want to know what’s inside?
- The WORD on ARM’s big.LITTLE Cortex-A15/A7 design philosophy from Jack Ganssle, a leading expert and consultant on embedded design and firmware development
- 3D Thursday: Cypress subsidiary Deca Technologies is onto making silicon interposers for 2.5D packaging in a big way. What if 2.5D got really cheap?
- Between ASIC and microcontroller: It’s all about System Realization
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Tag Archives: GPU
AMD’s new Trinity APU (Accelerated Processing Unit) for laptops/notebooks is a poster child for IP-centric SoC design
Yesterday, AMD introduced its second generation of A-series APUs (Accelerated Processing Units) that combine two to four Piledriver x86 microprocessor cores—each with 2Mbytes of L2 cache memory—with a Radeon 7000 GPU (Graphics Processing Unit), an HD Media Accelerator, a display … Continue reading
Posted in 32nm, EDA360, Silicon Realization, SoC, SoC Realization
Tagged Advanced Micro Devices, AMD, APU, DDR3, GPU, PCI Express, PCIe, Radeon
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3D Thursday: Qualcomm’s Nick Yu says “3D DRAM stacking has started—it’s shipping in products”
Today’s GSA Silicon Summit held at the Computer History Museum in Mountain View, California included a talk on 3D IC assembly by Nick Yu, VP of Engineering, VLSI Engineering, at Qualcomm. Yu is in charge of Qualcomm’s technology roadmaps including … Continue reading
Posted in 2.5D, 3D, EDA360, Silicon Realization, SoC, SoC Realization, System Realization
Tagged DDR SDRAM, GPU, JEDEC, SDRAM, Three-dimensional integrated circuit, Wide I/O
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Qualcomm reveals more Snapdragon 4 SoC details in a White Paper. Want to know what’s inside?
As I reported by the EDA360 Insider more than two months ago—see “Qualcomm renames existing ARM-based Snapdragon mobile application processors and provides future roadmap”—Qualcomm has been discussing the 28nm version of its Snapdragon mobile SoC, called the Snapdragon 4. Now … Continue reading
Posted in 28nm, ARM, EDA360, Silicon Realization, SoC, SoC Realization
Tagged GPU, Graphics processing unit, Krait, Nvidia, Qualcomm, Snapdragon, Wi-Fi
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3D Thursday: AMD Radeon E6460 embedded graphics processor employs two kinds of 3D assembly. One may really surprise you
Earlier this week, AMD launched the Radeon E6460 embedded GPU (graphics processor, see photo below). It’s an entry-level GPU with more than 2x the performance of the previous-generation Radeon E2400 GPU. To get the desired performance from this GPU—it’s capable … Continue reading
Friday Video: Webinar of NVIDIA GPU talk now online
A couple of days ago, I wrote a blog entry on Michael Shebanow’s GPU talk given to the local IEEE Computer at Cadence. (See “What would you do with a 23,000-simultaneous-thread school of piranha?…asks NVIDIA.”) Now, you can watch the recorded … Continue reading
Learn the secrets of taming the GPU—free—next Tuesday, September 13
Next Tuesday evening in San Jose, Michael Shebanow will give a talk titled “GPU computing: Taming a 23,000 Thread Beast!” Shebanow is a principal research scientist at NVIDIA and he’s got a lot of processor architectures under his belt—the 32-bit … Continue reading
Posted in EDA360, Silicon Realization, SoC Realization, System Realization
Tagged Fermi, GPU, IEEE, Nvidia, Tesla
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