Tag Archives: HMC

3D Thursday: Micron to present Hybrid Memory Cube status at EDPS in Monterey, April 6—there’s a lot of news

Posted on March 29, 2012 by

I’ve already written many blog entries about the Micron Hybrid Memory Cube (HMC), a 3D stacked memory device that can deliver a theoretical DRAM bandwidth of 128Gbytes/sec to a host system using a 4-die stack of DRAM (NOT SDRAM) on … Continue reading →

Posted in 3D, EDA360, Silicon Realization, SoC, SoC Realization | Tagged , , , | Leave a comment

3D Thursday: Let’s end 2011 with a high-performance DRAM memory stack design. How would you improve it?

Posted on December 28, 2011 by

For the last 3D Thursday blog post of 2011in the EDA360 Insider, I thought I’d take a flight of fancy and try to put as many of this year’s 3D IC concepts as possible together to see what we might … Continue reading →

Posted in 2.5D, 3D, EDA360, Memory, SoC, SoC Realization, System Realization | Tagged , , , , , , | Leave a comment

3D Thursday: Hybrid Memory Cube—wide I/O only more so—gets an industry consortium

Posted on October 13, 2011 by

Back in August, I wrote about the 3D SDRAM assembly called the Micron Hybrid Memory Cube (HMC, see “Want to know more about the Micron Hybrid Memory Cube (HMC)? How about its terabit/sec data rate?”) and I called it a … Continue reading →

Posted in 3D, EDA360, Memory, Samsung, SoC Realization | Tagged , , , , , , | Leave a comment