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Recent Posts
- A head-to-head comparison of the ARM Cortex-M4 and –M0 processor cores by Jack Ganssle
- Friday Video: SoC in tiny 500mg backpack transforms cockroach into radio-controlled exploration vehicle
- Friday Video: A different kind of fab with some very, very cool machines
- Friday Video: Get the latest skinny on the IPC-2581 open interchange standard for PCB design
- Smartphones: Where PCIe has not gone before—but will. Sooner rather than later.
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Top Posts
- A head-to-head comparison of the ARM Cortex-M4 and –M0 processor cores by Jack Ganssle
- 3D Thursday: Altera adds Avago MicroPOD optical interconnects to FPGA package to handle bidirectional 100Gbps Ethernet
- Qualcomm reveals more Snapdragon 4 SoC details in a White Paper. Want to know what’s inside?
- ARM drops Cortex-A7 core on unsuspecting market, devastates low-power SoC and application-processor landscapes. What’s it all mean?
- Download a free PDF of the Mixed-signal Methodology Guide, Chapter 1: Design Trends and Challenges
- How Skyera developed the 44Tbyte, enterprise-class Skyhawk SSD from the ground up. A System Realization story.
- EDA360 and the brand new Hewlett-Packard 15C Limited Edition RPN pocket scientific calculator
- Ingenious architectural features allow ST to extract maximum performance from new microcontroller family based on ARM Cortex-M4. Cost: less than 6 bucks in 1000s
- Who wants more technical detail on the Altera SoC FPGA? Altera says…you!
- By the numbers: 20nm (and 40nm, 32nm, 28nm, and 14nm) design to be discussed in technical detail at next week’s CDNLive! conference in Silicon Valley
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Tag Archives: IC
3D Thursday: EDPS conference features 3D Friday
The Electronic Design Process Symposium soon to be held in Monterey, California, will devote all of Friday, April 6 to 3D IC issues. There will be three morning presentations and a 5-person panel in the afternoon. The EDPS Program Web … Continue reading
Posted in 2.5D, 3D, EDA360, Silicon Realization, SoC, SoC Realization, System Realization
Tagged 3D, EDPS, IC
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3D Thursday: Mark LaPedus writes overview of the 3D IC landscape
Briefly noted: Over at the Semiconductor Manufacturing & Design Community, Senior Editor Mark LaPedus has just published an article that’s a good review of the various challenges to 3D IC adoption including: Known good die Testability Design for test Standards … Continue reading
Posted in 2.5D, 3D, EDA360, Silicon Realization, SoC, SoC Realization
Tagged 3D, DFT, IC, testability
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3D Thursday: Lessons learned from the IMEC’s 3D DRAM-on-logic chip design work
I recently covered the groundbreaking WIOMING 3D chip design done by CEA-Imec in conjunction with ST-Ericsson. (See “3D Week: Wide I/O SDRAM, Network on Chip, Multicore, TSV, Asynchronous Logic—3D SoC stack from CEA-Leti and ST-Ericsson hits all the advanced notes. … Continue reading
3D Week: The three interconnect crises of the electronics industry and the inevitability of 3D. Believable?
Many people in the electronics industry view 3D IC assembly as not being in the mainstream. That’s easy to understand. It’s not at the moment. Yet I do believe in the inevitability of 3D assembly. Here’s why. At last week’s … Continue reading
Posted in 2.5D, 3D, EDA360, Silicon Realization, SoC, SoC Realization, System Realization
Tagged 2.5D, 3D, IC, packaging
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3D Thursday (early): Steve’s Improbable History of 3D ICs? Six decades of 3D electronic packaging
Last week at the 9th International SoC Conference in Newport Beach, I moderated a 3D IC panel that did a great job of exploring today’s state of the art for 3D IC development. I will be blogging the presentations made … Continue reading
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