Tag Archives: IEEE 1149.1

DFT for 3D-IC: It’s déjà vu all over again

Reading Richard Goering’s blog about the Cadence-Imec collaboration on 3D-IC design for test architecture—How Imec and Cadence “Wrapped Up” 3D-IC Test—gave me a strong sense of déjà vu all over again. (Never pass up a chance to quote the great … Continue reading

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