Tag Archives: IEEE 1500

DFT for 3D-IC: It’s déjà vu all over again

Reading Richard Goering’s blog about the Cadence-Imec collaboration on 3D-IC design for test architecture—How Imec and Cadence “Wrapped Up” 3D-IC Test—gave me a strong sense of déjà vu all over again. (Never pass up a chance to quote the great … Continue reading


Posted in 3D, EDA360, Packaging, Silicon Realization | Tagged , , , , | Leave a comment