Tag Archives: IEEE 1801

Power-intent methodologies: Can’t we all just get along?

All ASIC and SoC designs are low-power designs at or below the 45nm node. For that reason alone, the industry has seen the rise of power-intent descriptions to help SoC and Silicon Realization teams develop new chip designs. For the … Continue reading

Posted in EDA360, Low Power, Silicon Realization, SoC, SoC Realization | Tagged , , , , , , | Leave a comment