Tag Archives: Imec

3D Thursday: Lessons learned from the IMEC’s 3D DRAM-on-logic chip design work

Posted on February 9, 2012 by

I recently covered the groundbreaking WIOMING 3D chip design done by CEA-Imec in conjunction with ST-Ericsson. (See “3D Week: Wide I/O SDRAM, Network on Chip, Multicore, TSV, Asynchronous Logic—3D SoC stack from CEA-Leti and ST-Ericsson hits all the advanced notes. … Continue reading →

Posted in 2.5D, 3D, EDA360, imec, SoC, SoC Realization | Tagged , , , , , , , , , , , , , , , | Leave a comment

3D Thursday: TSMC’s 3D plans and the word on 3D from Xilinx, Nvidia, IMEC, and STATS ChipPAC

Posted on January 12, 2012 by

For another take on last month’s RTI 3D conference held in Burlingame, CA, see Dr. Phil Garrou’s blog on the ElectroIQ site. Click here. For previous EDA360 Insider coverage of this event, see “3D Week: Wide I/O SDRAM, Network on … Continue reading →

Posted in 3D, EDA360, Silicon Realization, SoC Realization, System Realization, TSMC | Tagged , , , , | Leave a comment

3D Thursday: Low-cost, all-day workshop on 3D IC to be held in Newport Beach, December 9. Early bird discount ends November 25

Posted on November 3, 2011 by

This has to be the 3D IC educational bargain for this year. The Orange County Chapter of the IEEE Components, Packaging and Manufacturing Technology (CPMT) Society is sponsoring an all-day workshop on 3D IC technology on December 9, 2011. The … Continue reading →

Posted in 3D, EDA360, Silicon Realization | Tagged , , , | Leave a comment

DFT for 3D-IC: It’s déjà vu all over again

Posted on August 2, 2011 by

Reading Richard Goering’s blog about the Cadence-Imec collaboration on 3D-IC design for test architecture—How Imec and Cadence “Wrapped Up” 3D-IC Test—gave me a strong sense of déjà vu all over again. (Never pass up a chance to quote the great … Continue reading →

Posted in 3D, EDA360, Packaging, Silicon Realization | Tagged , , , , | Leave a comment

3D Thursday: IMEC prototypes 3D chip stack, finds some thermal surprises

Posted on July 14, 2011 by

Imec and several of its 3D integration partners (Globalfoundries, Intel, Micron, Panasonic, Samsung, TSMC, Fujitsu, Sony, Amkor, and Qualcomm) have fabricated a 3-chip 3D IC stack demonstration prototype with the intent of proving several assembly methods plus electrical characteristics and … Continue reading →

Posted in 3D, Silicon Realization, SoC Realization, System Realization, TSMC, TSV | Tagged , , , , , , , , , , | 1 Comment