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Top Posts
- A head-to-head comparison of the ARM Cortex-M4 and –M0 processor cores by Jack Ganssle
- AppliedMicro demos FPGA emulation of multicore server chip based on new 64-bit ARMv8 architecture
- Ingenious architectural features allow ST to extract maximum performance from new microcontroller family based on ARM Cortex-M4. Cost: less than 6 bucks in 1000s
- Realizing the ARM Cortex-A15: What does the road to 2.5GHz look like?
- Qualcomm reveals more Snapdragon 4 SoC details in a White Paper. Want to know what’s inside?
- Who wants more technical detail on the Altera SoC FPGA? Altera says…you!
- More news on the asymmetric processing SoC front
- Friday Video: Xtreme Embedded Design—A fully operational, 1/6-scale Atari Star Wars Arcade machine
- Want to know more about the Micron Hybrid Memory Cube (HMC)? How about its terabit/sec data rate?
- The DDR4 SDRAM spec and SoC design. What do we know now?
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Tag Archives: Imec
3D Thursday: Lessons learned from the IMEC’s 3D DRAM-on-logic chip design work
I recently covered the groundbreaking WIOMING 3D chip design done by CEA-Imec in conjunction with ST-Ericsson. (See “3D Week: Wide I/O SDRAM, Network on Chip, Multicore, TSV, Asynchronous Logic—3D SoC stack from CEA-Leti and ST-Ericsson hits all the advanced notes. … Continue reading
3D Thursday: TSMC’s 3D plans and the word on 3D from Xilinx, Nvidia, IMEC, and STATS ChipPAC
For another take on last month’s RTI 3D conference held in Burlingame, CA, see Dr. Phil Garrou’s blog on the ElectroIQ site. Click here. For previous EDA360 Insider coverage of this event, see “3D Week: Wide I/O SDRAM, Network on … Continue reading
Posted in 3D, EDA360, Silicon Realization, SoC Realization, System Realization, TSMC
Tagged Imec, Nvidia, STATS ChipPAC, TSMC, Xilinx
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3D Thursday: Low-cost, all-day workshop on 3D IC to be held in Newport Beach, December 9. Early bird discount ends November 25
This has to be the 3D IC educational bargain for this year. The Orange County Chapter of the IEEE Components, Packaging and Manufacturing Technology (CPMT) Society is sponsoring an all-day workshop on 3D IC technology on December 9, 2011. The … Continue reading
DFT for 3D-IC: It’s déjà vu all over again
Reading Richard Goering’s blog about the Cadence-Imec collaboration on 3D-IC design for test architecture—How Imec and Cadence “Wrapped Up” 3D-IC Test—gave me a strong sense of déjà vu all over again. (Never pass up a chance to quote the great … Continue reading
Posted in 3D, EDA360, Packaging, Silicon Realization
Tagged Cadence, IEEE 1149.1, IEEE 1500, Imec, JTAG
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3D Thursday: IMEC prototypes 3D chip stack, finds some thermal surprises
Imec and several of its 3D integration partners (Globalfoundries, Intel, Micron, Panasonic, Samsung, TSMC, Fujitsu, Sony, Amkor, and Qualcomm) have fabricated a 3-chip 3D IC stack demonstration prototype with the intent of proving several assembly methods plus electrical characteristics and … Continue reading
Posted in 3D, Silicon Realization, SoC Realization, System Realization, TSMC, TSV
Tagged Amkor, Fujitsu, GlobalFoundries, Imec, Intel, Micron, Panasonic, Qualcomm, Samsung, Sony, TSMC
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