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Recent Posts
- A head-to-head comparison of the ARM Cortex-M4 and –M0 processor cores by Jack Ganssle
- Friday Video: SoC in tiny 500mg backpack transforms cockroach into radio-controlled exploration vehicle
- Friday Video: A different kind of fab with some very, very cool machines
- Friday Video: Get the latest skinny on the IPC-2581 open interchange standard for PCB design
- Smartphones: Where PCIe has not gone before—but will. Sooner rather than later.
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Top Posts
- A head-to-head comparison of the ARM Cortex-M4 and –M0 processor cores by Jack Ganssle
- Ingenious architectural features allow ST to extract maximum performance from new microcontroller family based on ARM Cortex-M4. Cost: less than 6 bucks in 1000s
- My workbench from 1978 highlighted in EETimes as one of engineering’s messiest desks
- EDA360 and the brand new Hewlett-Packard 15C Limited Edition RPN pocket scientific calculator
- The DDR4 SDRAM spec and SoC design. What do we know now?
- ARM adds ARM Cortex-A15 and Cortex-R5 models to Fast Models 6.1 release, making these cores immediately available to System Realization teams
- Power, Performance, Cost. FDSOI lets you pick any three. Want proof? How about an ARM Cortex-M0 processor core example?
- Friday Video: How the iPhone saved a Corning glass factory in Harrodsburg, Kentucky
- Friday Video: Engineering humor from Don McMillan, the chip designer turned professional comedian
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Tag Archives: IP Integration
Tales from the EDA CEOs: The EDAC panel talks about IP and SoC integration, power, and other topics
Richard Goering has written up last week’s EDA CEO panel, sponsored by EDAC (the EDA Consortium). The panel took place at the Silicon Valley Bank’s headquarters in Santa Clara, California and featured CEOs from four EDA companies—Cadence (Lip-Bu Tan), Gradient … Continue reading
Posted in 3D, Apps, EDA360, Silicon Realization, SoC, SoC Realization, System Realization
Tagged 3D, Cadence, EDA, IP, IP Integration, Lego, Low Power, Mentor Graphics, Synopsys
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