Tag Archives: ISQED

Scaling the peaks to look at the 14nm cliff, Part 2: Tom Beckley from Cadence explains how we’re getting to 20nm and then on to 14nm and 10nm

This week at the ISQED Symposium in Silicon Valley, Tom Beckley who is the Senior VP of R&D for Custom IC and Signoff at Cadence opened the conference with a keynote covering  the industry’s challenges and progress at 20nm and … Continue reading

Posted in 10nm, 14nm, 20nm, 28nm, Design Abstraction, Design Intent, DFM, Double Patterning, EDA360, IBM, Silicon Realization | Tagged , , , , , , , , | Leave a comment

Scaling the 20nm peaks to look at the 14nm cliff, Part 1: Tom Beckley from Cadence maps the challenges of advanced node design at ISQED

Yesterday at the ISQED Symposium in Silicon Valley, Tom Beckley who is the Senior VP of R&D for Custom IC and Signoff at Cadence opened the conference with a keynote that lays out the challenges for IC designers tackling advanced … Continue reading

Posted in 14nm, 20nm, EDA360, Silicon Realization, SoC, SoC Realization | Tagged , , , | 1 Comment