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Recent Posts
- A head-to-head comparison of the ARM Cortex-M4 and –M0 processor cores by Jack Ganssle
- Friday Video: SoC in tiny 500mg backpack transforms cockroach into radio-controlled exploration vehicle
- Friday Video: A different kind of fab with some very, very cool machines
- Friday Video: Get the latest skinny on the IPC-2581 open interchange standard for PCB design
- Smartphones: Where PCIe has not gone before—but will. Sooner rather than later.
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Top Posts
- A head-to-head comparison of the ARM Cortex-M4 and –M0 processor cores by Jack Ganssle
- Ingenious architectural features allow ST to extract maximum performance from new microcontroller family based on ARM Cortex-M4. Cost: less than 6 bucks in 1000s
- Power, Performance, Cost. FDSOI lets you pick any three. Want proof? How about an ARM Cortex-M0 processor core example?
- Intel says Moore’s Law alive and well and living at 32nm
- Agilent knocks one out of the park with new, low-cost line of digital scopes—a very competitive entry into the low-end DSO market and a perfect example of EDA360 design using end-to-end design and apps.
- My workbench from 1978 highlighted in EETimes as one of engineering’s messiest desks
- The DDR4 SDRAM spec and SoC design. What do we know now?
- ARM adds ARM Cortex-A15 and Cortex-R5 models to Fast Models 6.1 release, making these cores immediately available to System Realization teams
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Tag Archives: Jeff Bier
Does your next SoC design include a “constellation of coprocessors”?
Jeff Bier is one of the industry’s most insightful observers and his specialty is digital signal processing, which includes graphics, image, and video processing these days in addition to the original definition that sort of included audio, radar, and sonar … Continue reading
Posted in EDA360, Mobile, SoC, SoC Realization, System Realization
Tagged DSP, heterogeneous processing, Jeff Bier
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