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Recent Posts
- A head-to-head comparison of the ARM Cortex-M4 and –M0 processor cores by Jack Ganssle
- Friday Video: SoC in tiny 500mg backpack transforms cockroach into radio-controlled exploration vehicle
- Friday Video: A different kind of fab with some very, very cool machines
- Friday Video: Get the latest skinny on the IPC-2581 open interchange standard for PCB design
- Smartphones: Where PCIe has not gone before—but will. Sooner rather than later.
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Top Posts
- The DDR4 SDRAM spec and SoC design. What do we know now?
- A head-to-head comparison of the ARM Cortex-M4 and –M0 processor cores by Jack Ganssle
- Want to know what’s going to happen at 20nm, 14nm, and beyond? A few answers from Frank Leu of Cadence
- 3D Thursday: Intel Penwell SoC for mobile phones employs POP (package-on-package) LPDDR2 SDRAM to reduce power
- Collaboration is key to making DFM work at 28nm and below
- Scaling the peaks to look at the 14nm cliff, Part 2: Tom Beckley from Cadence explains how we’re getting to 20nm and then on to 14nm and 10nm
- 3D Thursday: Lessons learned from the IMEC’s 3D DRAM-on-logic chip design work
- Friday Video: Exclusive iOS 5 preview from Apple and master magician Simon Pierro
- 3D Thursday: How about a closeup of the Avago MiniPOD optical interconnect on the Altera Optical FPGA?
- Are FinFETs inevitable at 20nm? “Yes, no, maybe” says Professor Chenming Hu
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