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Recent Posts
- A head-to-head comparison of the ARM Cortex-M4 and –M0 processor cores by Jack Ganssle
- Friday Video: SoC in tiny 500mg backpack transforms cockroach into radio-controlled exploration vehicle
- Friday Video: A different kind of fab with some very, very cool machines
- Friday Video: Get the latest skinny on the IPC-2581 open interchange standard for PCB design
- Smartphones: Where PCIe has not gone before—but will. Sooner rather than later.
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2.5D 3D 3D IC 20nm 28nm 32nm 40nm Agilent Altera AMD Analog Android Apple ARM ARM architecture ARM Cortex-A15 ASIC Broadcom Cadence Canon Cortex Cortex-A15 Cortex-M0 DAC Dave Jones DDR3 DDR4 Double Patterning EDA EDPS Field-programmable gate array FinFET Flash Flash memory FPGA Freescale Freescale Semiconductor GlobalFoundries Google IBM Intel IP iPad iPhone JEDEC Jim Hogan Kinect Linux Low Power Lytro microcontroller Micron Microsoft Mixed Signal Multi-core processor Nvidia OrCAD pcb Printed circuit board Qualcomm Robot Samsung SDRAM Snapdragon SoC STMicroelectronics SystemC Texas Instruments TI TSMC USB verification video Wide I/O XilinxTop Posts
- GLOBALFOUNDRIES’ 28nm process comes in three flavors. Which is right for you?
- A head-to-head comparison of the ARM Cortex-M4 and –M0 processor cores by Jack Ganssle
- Ingenious architectural features allow ST to extract maximum performance from new microcontroller family based on ARM Cortex-M4. Cost: less than 6 bucks in 1000s
- The DDR4 SDRAM spec and SoC design. What do we know now?
- 3D Thursday: Intel and FinFETs (Tri-Gate transistors)—a different kind of 3D
- What can you do with 45nm SOI? A lot, it turns out
- The WORD on ARM’s big.LITTLE Cortex-A15/A7 design philosophy from Jack Ganssle, a leading expert and consultant on embedded design and firmware development
- How do virtual prototyping, emulation, and FPGA prototyping differ? Answers from Frank Schirrmeister
- There’s a solar eclipse coming. Here’s a test shot from a Canon 60D dSLR, a Spiratone 400mm Sharpshooter, and a 2x telextender.
- Are FinFETs inevitable at 20nm? “Yes, no, maybe” says Professor Chenming Hu
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Tag Archives: Marc Greenberg
3D Thursday: Wide I/O and TSVs have a ripple effect on the DRAM controller. Who knew?
Currently, the JEDEC Wide I/O DRAM specification looks to be the biggest driving force behind the adoption of 3D IC assembly. The 512-bit data maw of a Wide I/O SDRAM provides high bandwidth with low power levels, both excellent arguments … Continue reading
Posted in 2.5D, 3D, DAC, EDA360, IP, Silicon Realization, SoC, SoC Realization, System Realization, TSV, Wide I/O
Tagged DRAM, JEDEC, Marc Greenberg, Mobile device, SDRAM, Wide I/O
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