Tag Archives: Mentor Graphics

You have six weeks to wait for the Semico IP Summit. What will you do until then?

Use of IP in the design of SoCs has long been a fact. The very name “SoC” says that you’re using microprocessor IP at the very least. With that comes memory IP, memory controller IP, interface IP, analog IP, etc. … Continue reading

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Is Low-Power design worth the costs? Live, sort of, from DVCon

Last week at DVCon, Cadence sponsored a low-power-themed lunch with the promise “Earn Your Degree in the Low-Power Arts and Sciences.” The panel consisted of: Qi Wang, technical marketing group director, Cadence Ruggero Castagnetti, distinguished engineer, LSI Corp. Sushma Honnavara … Continue reading

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Tales from the EDA CEOs: The EDAC panel talks about IP and SoC integration, power, and other topics

Richard Goering has written up last week’s EDA CEO panel, sponsored by EDAC (the EDA Consortium). The panel took place at the Silicon Valley Bank’s headquarters in Santa Clara, California and featured CEOs from four EDA companies—Cadence (Lip-Bu Tan), Gradient … Continue reading

Posted in 3D, Apps, EDA360, Silicon Realization, SoC, SoC Realization, System Realization | Tagged , , , , , , , , | Leave a comment